@@ -74,24 +74,25 @@ class InputCapture {
7474 timer->instance ->tim ->SR = 0 ;
7575
7676 // HAL_TIM_IC_Start_IT(instance.peripheral->handle, instance.channel_rising)
77+ volatile HAL_TIM_ChannelStateTypeDef* chx_1_state;
78+ volatile HAL_TIM_ChannelStateTypeDef* chx_1_n_state;
79+ uint32_t enableCCx_1;
7780 {
78- volatile HAL_TIM_ChannelStateTypeDef* ch_state =
79- &timer->instance ->hal_tim
81+ chx_1_state = &timer->instance ->hal_tim
8082 ->ChannelState [TimerDomain::get_channel_state_idx (pin_rising.channel )];
81- volatile HAL_TIM_ChannelStateTypeDef* n_ch_state =
82- &timer->instance ->hal_tim
83+ chx_1_n_state = &timer->instance ->hal_tim
8384 ->ChannelNState [TimerDomain::get_channel_state_idx (pin_rising.channel )];
84- if ((*ch_state != HAL_TIM_CHANNEL_STATE_READY) ||
85- (*n_ch_state != HAL_TIM_CHANNEL_STATE_READY)) {
85+ if ((*chx_1_state != HAL_TIM_CHANNEL_STATE_READY) ||
86+ (*chx_1_n_state != HAL_TIM_CHANNEL_STATE_READY)) {
8687 ErrorHandler (" Channels not ready" );
8788 return ;
8889 }
8990
90- *ch_state = HAL_TIM_CHANNEL_STATE_BUSY;
91- *n_ch_state = HAL_TIM_CHANNEL_STATE_BUSY;
91+ *chx_1_state = HAL_TIM_CHANNEL_STATE_BUSY;
92+ *chx_1_n_state = HAL_TIM_CHANNEL_STATE_BUSY;
9293
9394 timer->template enable_capture_compare_interrupt <pin_rising.channel >();
94- uint32_t enableCCx = TIM_CCER_CC1E
95+ enableCCx_1 = TIM_CCER_CC1E
9596 << (TimerDomain::get_channel_mul4 (pin_rising.channel ) & 0x1FU
9697 ); /* 0x1FU = 31 bits max shift */
9798 SET_BIT (timer->instance ->tim ->CCER , enableCCx);
@@ -106,8 +107,13 @@ class InputCapture {
106107 &timer->instance ->hal_tim
107108 ->ChannelNState [TimerDomain::get_channel_state_idx (channel_falling)];
108109 if ((*ch_state != HAL_TIM_CHANNEL_STATE_READY) ||
109- (*n_ch_state != HAL_TIM_CHANNEL_STATE_READY)) {
110+ (*n_ch_state != HAL_TIM_CHANNEL_STATE_READY)) [[unlikely]] {
110111 ErrorHandler (" Channels not ready" );
112+
113+ timer->template disable_capture_compare_interrupt <pin_rising.channel >();
114+ CLEAR_BIT (timer->instance ->tim ->CCER , enableCCx_1);
115+ *chx_1_state = HAL_TIM_CHANNEL_STATE_READY;
116+ *chx_1_n_state = HAL_TIM_CHANNEL_STATE_READY;
111117 return ;
112118 }
113119
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