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8 | 8 | #ifndef MPU_HPP |
9 | 9 | #define MPU_HPP |
10 | 10 |
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11 | | -#ifndef HALAL_MPUBUFFERS_MAX_INSTANCES |
| 11 | +#ifndef HALAL_MPUBUFFERS_MAX_INSTANCES // Define this in you build system if you need a different value |
12 | 12 | #define HALAL_MPUBUFFERS_MAX_INSTANCES 100 |
13 | 13 | #endif |
14 | 14 |
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@@ -76,8 +76,8 @@ struct MPUDomain { |
76 | 76 | } |
77 | 77 |
|
78 | 78 | template <class Ctx> |
79 | | - consteval void inscribe(Ctx &ctx) const { |
80 | | - ctx.template add<MPUDomain>(e, this); |
| 79 | + consteval std::size_t inscribe(Ctx &ctx) const { |
| 80 | + return ctx.template add<MPUDomain>(e, this); |
81 | 81 | } |
82 | 82 | }; |
83 | 83 |
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@@ -127,7 +127,7 @@ struct MPUDomain { |
127 | 127 | else if (cfg.domain == MemoryDomain::D3) sizes.d3_nc_size = cfg.mpu_region_size; |
128 | 128 | } |
129 | 129 | } |
130 | | - // Align totals to 32 bytes |
| 130 | + // Align totals to 32 bytes (max possible alignment, just in case) |
131 | 131 | sizes.d1_total = align_up(sizes.d1_total, 32); |
132 | 132 | sizes.d2_total = align_up(sizes.d2_total, 32); |
133 | 133 | sizes.d3_total = align_up(sizes.d3_total, 32); |
@@ -379,6 +379,34 @@ struct MPUDomain { |
379 | 379 | MPU_InitStruct.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; // This should be scrutinized to see why it was non-bufferable before changing to bufferable |
380 | 380 | HAL_MPU_ConfigRegion(&MPU_InitStruct); |
381 | 381 |
|
| 382 | + // DTCM RAM (Cached) |
| 383 | + MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
| 384 | + MPU_InitStruct.Number = MPU_REGION_NUMBER10; |
| 385 | + MPU_InitStruct.BaseAddress = 0x20000000; |
| 386 | + MPU_InitStruct.Size = MPU_REGION_SIZE_128KB; |
| 387 | + MPU_InitStruct.SubRegionDisable = 0x0; |
| 388 | + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; |
| 389 | + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 390 | + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; // DTCM is not effective for code exec |
| 391 | + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; |
| 392 | + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; |
| 393 | + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; |
| 394 | + HAL_MPU_ConfigRegion(&MPU_InitStruct); |
| 395 | + |
| 396 | + // ITCM RAM + Shared ITCM/AXI (0x00000000 - 0x0003FFFF = 256KB total) Executable, Critical Code / Vector Table |
| 397 | + MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
| 398 | + MPU_InitStruct.Number = MPU_REGION_NUMBER11; |
| 399 | + MPU_InitStruct.BaseAddress = 0x00000000; |
| 400 | + MPU_InitStruct.Size = MPU_REGION_SIZE_256KB; // 64KB ITCM + 192KB Shared (with AXI) |
| 401 | + MPU_InitStruct.SubRegionDisable = 0x0; |
| 402 | + MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; |
| 403 | + MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 404 | + MPU_InitStruct.DisableExec = MPU_INSTRUCTION_ACCESS_ENABLE; |
| 405 | + MPU_InitStruct.IsShareable = MPU_ACCESS_SHAREABLE; |
| 406 | + MPU_InitStruct.IsCacheable = MPU_ACCESS_CACHEABLE; |
| 407 | + MPU_InitStruct.IsBufferable = MPU_ACCESS_BUFFERABLE; |
| 408 | + HAL_MPU_ConfigRegion(&MPU_InitStruct); |
| 409 | + |
382 | 410 | // D1 RAM (Cached) |
383 | 411 | MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
384 | 412 | MPU_InitStruct.Number = MPU_REGION_NUMBER2; |
@@ -411,7 +439,7 @@ struct MPUDomain { |
411 | 439 | MPU_InitStruct.Enable = MPU_REGION_ENABLE; |
412 | 440 | MPU_InitStruct.Number = MPU_REGION_NUMBER8; |
413 | 441 | MPU_InitStruct.BaseAddress = 0x30000000; |
414 | | - MPU_InitStruct.Size = MPU_REGION_SIZE_512B; |
| 442 | + MPU_InitStruct.Size = MPU_REGION_SIZE_512B; // Should check if ethernet descriptors really use only this (linker script uses absolute addresses) |
415 | 443 | MPU_InitStruct.SubRegionDisable = 0x0; |
416 | 444 | MPU_InitStruct.TypeExtField = MPU_TEX_LEVEL0; |
417 | 445 | MPU_InitStruct.AccessPermission = MPU_REGION_FULL_ACCESS; |
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