From e9b9bad1a4bb33d6a7fb3868f979d59478eb603c Mon Sep 17 00:00:00 2001 From: Rot127 Date: Sun, 12 Oct 2025 11:22:21 -0500 Subject: [PATCH 01/16] Enable i686 Python libraries again. --- .github/workflows/build-wheels-publish.yml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/build-wheels-publish.yml b/.github/workflows/build-wheels-publish.yml index f5bb0f9448..252f053236 100644 --- a/.github/workflows/build-wheels-publish.yml +++ b/.github/workflows/build-wheels-publish.yml @@ -45,9 +45,9 @@ jobs: include: # NOTE: Making this to parallelize and speed up workflow # i686 - manylinux - # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp*-manylinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: i686, cibw_build: 'cp*-manylinux*', cibw_skip: '' } # i686 - musllinux - # - { os: ubuntu-latest, arch: i686, cibw_build: 'cp*-musllinux*', cibw_skip: '' } + - { os: ubuntu-latest, arch: i686, cibw_build: 'cp*-musllinux*', cibw_skip: '' } # x86_64 - manylinux - { os: ubuntu-latest, arch: x86_64, cibw_build: 'cp*-manylinux*', cibw_skip: '' } # x86_64 - musllinux @@ -63,7 +63,7 @@ jobs: # windows - amd64 - { os: windows-latest, arch: AMD64, cibw_build: 'cp*', cibw_skip: '' } # windows - x86 - # - { os: windows-latest, arch: x86, cibw_build: 'cp*', cibw_skip: '' } + - { os: windows-latest, arch: x86, cibw_build: 'cp*', cibw_skip: '' } # windows - arm64 - { os: windows-11-arm, arch: ARM64, cibw_build: 'cp*', cibw_skip: '*38* *39* *310*' } From 91fb17be0c61db19d8883c54ddc17010e923a100 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Wed, 29 Oct 2025 13:30:48 -0500 Subject: [PATCH 02/16] Enable Mips32 target to CI --- .github/workflows/CrossBuilds.yml | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/.github/workflows/CrossBuilds.yml b/.github/workflows/CrossBuilds.yml index 34a80e0df4..5429a83b73 100644 --- a/.github/workflows/CrossBuilds.yml +++ b/.github/workflows/CrossBuilds.yml @@ -47,17 +47,17 @@ jobs: packages: 'gcc-s390x-linux-gnu g++-s390x-linux-gnu binutils-s390x-linux-gnu libc6-dev-s390x-cross qemu-user-static', cross_file: 'cross_configs/linux_s390x_ubuntu24.cmake', } - # - { - # name: 'QEMU Linux Mips 32', - # os: ubuntu-24.04, - # arch: x64, - # build-system: 'cmake', - # diet-build: 'OFF', - # build_type: 'Debug', - # diet_build: false, - # packages: 'gcc-mips-linux-gnu g++-mips-linux-gnu binutils-mips-linux-gnu libc6-dev-mips-cross qemu-user-static', - # cross_file: 'cross_configs/linux_mips_ubuntu24.cmake', - # } + - { + name: 'QEMU Linux Mips 32', + os: ubuntu-24.04, + arch: x64, + build-system: 'cmake', + diet-build: 'OFF', + build_type: 'Debug', + diet_build: false, + packages: 'gcc-mips-linux-gnu g++-mips-linux-gnu binutils-mips-linux-gnu libc6-dev-mips-cross qemu-user-static', + cross_file: 'cross_configs/linux_mips_ubuntu24.cmake', + } - { name: 'QEMU Linux Mips64el', os: ubuntu-24.04, From 2387224b4bc30d0d306e75747fdc15b3eb03ae49 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 30 Oct 2025 10:04:44 -0500 Subject: [PATCH 03/16] Fix asm text test errors on 32bit machines --- arch/ARM/ARMInstPrinter.c | 15 +++++++++------ arch/X86/X86IntelInstPrinter.c | 2 +- suite/cstest/src/helper.c | 17 +++++++---------- 3 files changed, 17 insertions(+), 17 deletions(-) diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 3e547da528..132cff99ff 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -886,15 +886,17 @@ static inline void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) static inline void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) { add_cs_detail(MI, ARM_OP_GROUP_PImmediate, OpNum); - SStream_concat(O, "%s%d", "p", - MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); + SStream_concat( + O, "%s%" PRIu32, "p", + (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); } static inline void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) { add_cs_detail(MI, ARM_OP_GROUP_CImmediate, OpNum); - SStream_concat(O, "%s%d", "c", - MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); + SStream_concat( + O, "%s%" PRIu32, "c", + (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); } static inline void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) @@ -1364,8 +1366,9 @@ static inline void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) { add_cs_detail(MI, ARM_OP_GROUP_FBits16, OpNum); SStream_concat(O, "%s%s", markup("")); } diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index efd0511d15..f478abab40 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -1181,7 +1181,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) SStream_concat0(O, " + "); _printOperand(MI, Op + X86_AddrIndexReg, O); if (ScaleVal != 1) - SStream_concat(O, "*%u", ScaleVal); + SStream_concat(O, "*%" PRIu64, ScaleVal); NeedPlus = true; } diff --git a/suite/cstest/src/helper.c b/suite/cstest/src/helper.c index f3eccd550a..313973506f 100644 --- a/suite/cstest/src/helper.c +++ b/suite/cstest/src/helper.c @@ -2,11 +2,8 @@ /* By Do Minh Tuan , 02-2019 */ #include -#include #include -#include #include -#include #include #include #include @@ -91,9 +88,9 @@ void replace_negative(char *src, size_t src_len, size_t arch_bits) char *tmp, *result, *found, *origin, *orig_found; int cnt, valid; char *value, *tmp_tmp; - unsigned short int tmp_short; - unsigned int tmp_int; - unsigned long int tmp_long; + uint16_t tmp_short; + uint32_t tmp_int; + uint64_t tmp_long; result = (char *)malloc(sizeof(char)); result[0] = '\0'; @@ -124,11 +121,11 @@ void replace_negative(char *src, size_t src_len, size_t arch_bits) sscanf(value, "%hu", &tmp_short); add_str(&result, "%s%hu", tmp_tmp, tmp_short); } else if (arch_bits == 32) { - sscanf(value, "%u", &tmp_int); - add_str(&result, "%s%u", tmp_tmp, tmp_int); + sscanf(value, "%" PRIu32, &tmp_int); + add_str(&result, "%s%" PRIu32, tmp_tmp, tmp_int); } else if (arch_bits == 64) { - sscanf(value, "%lu", &tmp_long); - add_str(&result, "%s%lu", tmp_tmp, tmp_long); + sscanf(value, "%" PRIu64, &tmp_long); + add_str(&result, "%s%" PRIu64, tmp_tmp, tmp_long); } } else From 430c2c1bb8eff67b86cf3da9ec25c7a2a1fcb4dc Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 30 Oct 2025 10:26:47 -0500 Subject: [PATCH 04/16] Add ARM musl cross toolchainfile --- cross_configs/linux_arm_fedora42_musl.cmake | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 cross_configs/linux_arm_fedora42_musl.cmake diff --git a/cross_configs/linux_arm_fedora42_musl.cmake b/cross_configs/linux_arm_fedora42_musl.cmake new file mode 100644 index 0000000000..1bfa6f5234 --- /dev/null +++ b/cross_configs/linux_arm_fedora42_musl.cmake @@ -0,0 +1,19 @@ +# This example file is for ARMv7 cross builds on Fedora 42. +# The toolchain used is https://musl.cc/armv7m-linux-musleabi-cross.tgz +set(CMAKE_SYSTEM_NAME Linux) +set(CMAKE_SYSTEM_PROCESSOR arm) +set(CMAKE_C_COMPILE_OPTIONS_SYSROOT "--sysroot=") +set(CMAKE_CXX_COMPILE_OPTIONS_SYSROOT "--sysroot=") + +set(TOOLCHAIN_DIR /home/user/toolchains/armv7m-linux-musleabi-cross/) +set(CMAKE_C_COMPILER ${TOOLCHAIN_DIR}/bin/armv7m-linux-musleabi-gcc) +set(CMAKE_ASM_COMPILER ${TOOLCHAIN_DIR}/bin/armv7m-linux-musleabi-gcc) +set(CMAKE_CROSS_COMPILING 1) + +set(CMAKE_SYSROOT /home/user/toolchains/armv7m-linux-musleabi-cross/armv7m-linux-musleabi/) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +set(CMAKE_CROSSCOMPILING_EMULATOR qemu-arm-static;-L;${CMAKE_SYSROOT}) From 2e7dd9fe45d1a36d98bb1e6ae168d99db557078c Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 30 Oct 2025 10:28:28 -0500 Subject: [PATCH 05/16] Add Windows i686 cross build --- .github/workflows/CrossBuilds.yml | 12 ++++++++++++ cross_configs/windows_i686_ubuntu24.cmake | 13 +++++++++++++ tests/MC/AArch64/basic-a64-instructions.s.yaml | 2 +- 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 cross_configs/windows_i686_ubuntu24.cmake diff --git a/.github/workflows/CrossBuilds.yml b/.github/workflows/CrossBuilds.yml index 5429a83b73..1b49037fbf 100644 --- a/.github/workflows/CrossBuilds.yml +++ b/.github/workflows/CrossBuilds.yml @@ -80,6 +80,18 @@ jobs: packages: 'gcc-powerpc64-linux-gnu g++-powerpc64-linux-gnu binutils-powerpc64-linux-gnu libc6-dev-ppc64-cross qemu-user-static', cross_file: 'cross_configs/linux_ppc64_ubuntu24.cmake', } + - { + name: '[BUILD ONLY] Windows i686 mingw', + os: ubuntu-24.04, + arch: x64, + build-system: 'cmake', + diet-build: 'OFF', + build_type: 'Debug', + diet_build: false, + skip_tests: true, + packages: 'gcc-mingw-w64-i686 g++-mingw-w64-i686 mingw-w64-tools', + cross_file: 'cross_configs/windows_i686_ubuntu24.cmake', + } - { name: '[BUILD ONLY] Android 35 (arm64_v8a) NDK 29', os: ubuntu-24.04, diff --git a/cross_configs/windows_i686_ubuntu24.cmake b/cross_configs/windows_i686_ubuntu24.cmake new file mode 100644 index 0000000000..fec5d56783 --- /dev/null +++ b/cross_configs/windows_i686_ubuntu24.cmake @@ -0,0 +1,13 @@ +# This example file is for builds on Ubunutu 24.04. +set(CMAKE_SYSTEM_NAME Windows) +set(CMAKE_SYSTEM_PROCESSOR i686) + +set(CMAKE_C_COMPILER i686-w64-mingw32-gcc) +set(CMAKE_CXX_COMPILER i686-w64-mingw32-g++) +set(CMAKE_RC_COMPILER i686-w64-mingw32-windres) + +set(CMAKE_FIND_ROOT_PATH /usr/i686-w64-mingw32) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) diff --git a/tests/MC/AArch64/basic-a64-instructions.s.yaml b/tests/MC/AArch64/basic-a64-instructions.s.yaml index 3a5610389a..60e6406f30 100644 --- a/tests/MC/AArch64/basic-a64-instructions.s.yaml +++ b/tests/MC/AArch64/basic-a64-instructions.s.yaml @@ -4839,7 +4839,7 @@ test_cases: expected: insns: - - asm_text: "cbnz x3, #-4" + asm_text: "cbnz x3, #0xfffffffffffffffc" - input: From 885a8ecb064ad19ffb8d77d552fe4737e46c27a3 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 30 Oct 2025 11:11:17 -0500 Subject: [PATCH 06/16] More 32bit bug fixes --- arch/AArch64/AArch64InstPrinter.c | 6 +++--- arch/ARM/ARMInstPrinter.c | 6 +++--- arch/X86/X86ATTInstPrinter.c | 10 +++++----- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 84a5b6a6a9..29d00d6952 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -1131,7 +1131,7 @@ void printShifter(MCInst *MI, unsigned OpNum, SStream *O) AArch64_AM_getShiftValue(Val) == 0) return; SStream_concat( - O, "%s%s%s%s#%d", ", ", + O, "%s%s%s%s#%u", ", ", AArch64_AM_getShiftExtendName(AArch64_AM_getShiftType(Val)), " ", markup("")); @@ -1202,7 +1202,7 @@ static void printMemExtendImpl(bool SignExtend, bool DoShift, unsigned Width, if (getUseMarkup) SStream_concat0(O, ""); } @@ -2319,7 +2319,7 @@ void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O) unsigned Val = \ MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ SStream_concat(O, "%s", markup("")); \ } DEFINE_printComplexRotationOp(180, 90); diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 132cff99ff..1bb97de105 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -1367,8 +1367,8 @@ static inline void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) add_cs_detail(MI, ARM_OP_GROUP_FBits16, OpNum); SStream_concat(O, "%s%s", markup("")); } @@ -1627,7 +1627,7 @@ DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) OpNo, Angle, Remainder); \ unsigned Val = \ MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ - SStream_concat(O, "#%d", (Val * Angle) + Remainder); \ + SStream_concat(O, "#%u", (uint32_t)((Val * Angle) + Remainder)); \ } DEFINE_printComplexRotationOp(90, 0) DEFINE_printComplexRotationOp(180, 90) diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index b2c200714e..f52a030b0f 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -555,7 +555,7 @@ static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) if (val > HEX_THRESHOLD) SStream_concat(O, "$0x%x", val); else - SStream_concat(O, "$%u", val); + SStream_concat(O, "$%" PRIu8, val); if (MI->csh->detail_opt) { MI->flat_insn->detail->x86 @@ -745,7 +745,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) // do not print number in negative form imm = imm & 0xff; if (imm >= 0 && imm <= HEX_THRESHOLD) - SStream_concat(O, "$%u", imm); + SStream_concat(O, "$%" PRIu64, imm); else { SStream_concat(O, "$0x%x", imm); } @@ -768,7 +768,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) case X86_INS_XOR: // do not print number in negative form if (imm >= 0 && imm <= HEX_THRESHOLD) - SStream_concat(O, "$%u", imm); + SStream_concat(O, "$%" PRIu64, imm); else { imm = arch_masks[opsize ? opsize : MI->imm_size] & imm; @@ -780,7 +780,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) case X86_INS_RETF: // RET imm16 if (imm >= 0 && imm <= HEX_THRESHOLD) - SStream_concat(O, "$%u", imm); + SStream_concat(O, "$%" PRIu64, imm); else { imm = 0xffff & imm; SStream_concat(O, "$0x%x", imm); @@ -938,7 +938,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) .op_count] .mem.scale = (int)ScaleVal; if (ScaleVal != 1) { - SStream_concat(O, ", %u", ScaleVal); + SStream_concat(O, ", %" PRIu64, ScaleVal); } } From df0a93a0cea0512d02c295a5699798828763c77a Mon Sep 17 00:00:00 2001 From: Rot127 Date: Thu, 30 Oct 2025 11:18:03 -0500 Subject: [PATCH 07/16] Add cross build/testing for ARM. --- .github/workflows/CrossBuilds.yml | 11 +++++++++++ cross_configs/linux_arm_ubuntu24.cmake | 17 +++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 cross_configs/linux_arm_ubuntu24.cmake diff --git a/.github/workflows/CrossBuilds.yml b/.github/workflows/CrossBuilds.yml index 1b49037fbf..696bd707b9 100644 --- a/.github/workflows/CrossBuilds.yml +++ b/.github/workflows/CrossBuilds.yml @@ -80,6 +80,17 @@ jobs: packages: 'gcc-powerpc64-linux-gnu g++-powerpc64-linux-gnu binutils-powerpc64-linux-gnu libc6-dev-ppc64-cross qemu-user-static', cross_file: 'cross_configs/linux_ppc64_ubuntu24.cmake', } + - { + name: 'QEMU Linux ARM', + os: ubuntu-24.04, + arch: x64, + build-system: 'cmake', + diet-build: 'OFF', + build_type: 'Debug', + diet_build: false, + packages: 'gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static', + cross_file: 'cross_configs/linux_arm_ubuntu24.cmake', + } - { name: '[BUILD ONLY] Windows i686 mingw', os: ubuntu-24.04, diff --git a/cross_configs/linux_arm_ubuntu24.cmake b/cross_configs/linux_arm_ubuntu24.cmake new file mode 100644 index 0000000000..042758ca67 --- /dev/null +++ b/cross_configs/linux_arm_ubuntu24.cmake @@ -0,0 +1,17 @@ +# This example file is for builds on Ubunutu 24.04. +# sudo apt install gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static +set(CMAKE_SYSTEM_NAME Linux) +set(CMAKE_SYSTEM_PROCESSOR arm) + +set(CMAKE_C_COMPILER arm-linux-gnueabihf-gcc) +set(CMAKE_ASM_COMPILER arm-linux-gnueabihf-gcc) +set(CMAKE_CROSS_COMPILING 1) + +set(CMAKE_SYSROOT /usr/arm-linux-gnueabihf) + +set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) +set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) +set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) + +set(CMAKE_CROSSCOMPILING_EMULATOR qemu-arm-static;-L;${CMAKE_SYSROOT}) + From 6423bf0c99e08c21362a9503f4d4a8f635aad4e6 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 10 Feb 2026 00:51:36 +0100 Subject: [PATCH 08/16] Get rid of va_args. --- arch/AArch64/AArch64Mapping.c | 41 ++++++++++--------------------- arch/AArch64/AArch64Mapping.h | 2 +- arch/ARC/ARCMapping.c | 3 +-- arch/ARC/ARCMapping.h | 11 +++------ arch/ARM/ARMInstPrinter.c | 22 ++++++++--------- arch/ARM/ARMMapping.c | 12 +++------ arch/ARM/ARMMapping.h | 28 +++++++++++++++------ arch/LoongArch/LoongArchMapping.c | 3 +-- arch/LoongArch/LoongArchMapping.h | 11 +++------ arch/Mips/MipsMapping.c | 4 +-- arch/Mips/MipsMapping.h | 9 +++---- arch/SystemZ/SystemZMapping.c | 6 ++--- arch/SystemZ/SystemZMapping.h | 12 ++++----- 13 files changed, 70 insertions(+), 94 deletions(-) diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 29836fb9ff..c8e10f4b31 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -1653,7 +1653,7 @@ void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group, } else vas = get_vl_by_suffix(Dot[1]); AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE, - vas); + vas, 0, 0); break; } case AArch64_OP_GROUP_MatrixTileList: { @@ -1668,7 +1668,7 @@ void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE_LIST, AARCH64LAYOUT_VL_D, - (int)(AARCH64_REG_ZAD0 + I)); + (int)(AARCH64_REG_ZAD0 + I), 0); AArch64_inc_op_count(MI); } AArch64_get_detail(MI)->is_doing_sme = false; @@ -1976,7 +1976,7 @@ void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_Matrix_64: { unsigned EltSize = temp_arg_0; AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE, - (AArch64Layout_VectorLayout)EltSize); + (AArch64Layout_VectorLayout)EltSize, 0, 0); break; } case AArch64_OP_GROUP_MatrixIndex_0: @@ -1988,7 +1988,7 @@ void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_sme( MI, OpNum, AARCH64_SME_MATRIX_SLICE_OFF, AARCH64LAYOUT_INVALID, - (uint32_t)(MCInst_getOpVal(MI, OpNum) * scale)); + (uint32_t)(MCInst_getOpVal(MI, OpNum) * scale), 0); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { // The index is part of a predicate @@ -2017,7 +2017,7 @@ void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group, vas = get_vl_by_suffix(Dot[1]); setup_sme_operand(MI); AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE, - vas); + vas, 0, 0); AArch64_get_detail_op(MI, 0)->sme.is_vertical = isVertical; break; } @@ -2454,7 +2454,7 @@ void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg) (Reg >= AARCH64_REG_ZAB0 && Reg < AARCH64_REG_ZT0)) { // A tile register should be treated as SME operand. AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE, - sme_reg_to_vas(Reg)); + sme_reg_to_vas(Reg), 0, 0); return; } else if (((Reg >= AARCH64_REG_P0) && (Reg <= AARCH64_REG_P15)) || ((Reg >= AARCH64_REG_PN0) && (Reg <= AARCH64_REG_PN15))) { @@ -2466,7 +2466,7 @@ void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg) if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_SME) { AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_SLICE_REG, - AARCH64LAYOUT_INVALID); + AARCH64LAYOUT_INVALID, 0, 0); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { AArch64_set_detail_op_pred(MI, OpNum); @@ -2518,7 +2518,7 @@ void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum, AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_SLICE_OFF, AARCH64LAYOUT_INVALID, - (uint32_t)1); + (uint32_t)1, 0); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { AArch64_set_detail_op_pred(MI, OpNum); @@ -2720,7 +2720,7 @@ void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum) /// Adds a SME matrix component to a SME operand. void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, aarch64_sme_op_part part, - AArch64Layout_VectorLayout vas, ...) + AArch64Layout_VectorLayout vas, uint64_t arg_0, uint64_t arg_1) { if (!detail_is_set(MI)) return; @@ -2733,12 +2733,7 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, CS_ASSERT_RET(0); case AARCH64_SME_MATRIX_TILE_LIST: { setup_sme_operand(MI); - va_list args; - va_start(args, vas); - // NOLINTBEGIN(clang-analyzer-valist.Uninitialized) - int Tile = va_arg(args, int); - // NOLINTEND(clang-analyzer-valist.Uninitialized) - va_end(args); + int Tile = arg_0; AArch64_get_detail_op(MI, 0)->sme.type = AARCH64_SME_OP_TILE; AArch64_get_detail_op(MI, 0)->sme.tile = Tile; AArch64_get_detail_op(MI, 0)->vas = vas; @@ -2780,23 +2775,13 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, CS_ASSERT_RET( AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm == AARCH64_SLICE_IMM_INVALID); - va_list args; - va_start(args, vas); - // NOLINTBEGIN(clang-analyzer-valist.Uninitialized) - uint16_t offset = va_arg(args, uint32_t); - // NOLINTEND(clang-analyzer-valist.Uninitialized) - va_end(args); + uint16_t offset = arg_0; AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm = offset; break; } case AARCH64_SME_MATRIX_SLICE_OFF_RANGE: { - va_list args; - va_start(args, vas); - // NOLINTBEGIN(clang-analyzer-valist.Uninitialized) - uint8_t First = va_arg(args, uint32_t); - uint8_t Offset = va_arg(args, uint32_t); - // NOLINTEND(clang-analyzer-valist.Uninitialized) - va_end(args); + uint8_t First = arg_0; + uint8_t Offset = arg_1; AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first = First; AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.offset = diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index 2eb116eddf..85ff6930ac 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -75,7 +75,7 @@ void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, aarch64_op_type type); void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, aarch64_sme_op_part part, - AArch64Layout_VectorLayout vas, ...); + AArch64Layout_VectorLayout vas, uint64_t arg_0, uint64_t arg_1); void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum); void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index, aarch64_reg Reg, cs_ac_type access); diff --git a/arch/ARC/ARCMapping.c b/arch/ARC/ARCMapping.c index 5e31f3495f..3e84743153 100644 --- a/arch/ARC/ARCMapping.c +++ b/arch/ARC/ARCMapping.c @@ -209,12 +209,11 @@ void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg) ARC_inc_op_count(MI); } -void ARC_add_cs_detail(MCInst *MI, int op_group, va_list args) +void ARC_add_cs_detail(MCInst *MI, int op_group, size_t OpNum) { if (!detail_is_set(MI)) return; - unsigned OpNum = va_arg(args, unsigned); cs_op_type op_type = map_get_op_type(MI, OpNum); cs_op_type base_op_type = op_type; cs_op_type offset_op_type; diff --git a/arch/ARC/ARCMapping.h b/arch/ARC/ARCMapping.h index c92d06b1ea..6794554c03 100644 --- a/arch/ARC/ARCMapping.h +++ b/arch/ARC/ARCMapping.h @@ -39,16 +39,13 @@ void ARC_init_cs_detail(MCInst *MI); void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum, arc_op_type ImmType, int64_t Imm); void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group, - va_list args); + size_t op_num); static inline void add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group, - ...) + size_t op_num) { if (!detail_is_set(MI)) return; - va_list args; - va_start(args, op_group); - ARC_add_cs_detail(MI, op_group, args); - va_end(args); + ARC_add_cs_detail(MI, op_group, op_num); } -#endif \ No newline at end of file +#endif diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 1bb97de105..e4448effac 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -76,7 +76,7 @@ static inline void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup) { - add_cs_detail(MI, ARM_OP_GROUP_RegImmShift, ShOpc, ShImm); + add_cs_detail_2(MI, ARM_OP_GROUP_RegImmShift, -1, ShOpc, ShImm); if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) return; SStream_concat0(O, ", "); @@ -406,7 +406,7 @@ static inline void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, static inline void CONCAT(printAddrMode3Operand, AlwaysPrintImm0)( \ MCInst * MI, unsigned Op, SStream *O) \ { \ - add_cs_detail(MI, \ + add_cs_detail_1(MI, \ CONCAT(ARM_OP_GROUP_AddrMode3Operand, \ AlwaysPrintImm0), \ Op, AlwaysPrintImm0); \ @@ -486,7 +486,7 @@ static inline void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, static inline void CONCAT(printMveAddrModeRQOperand, shift)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail( \ + add_cs_detail_1( \ MI, CONCAT(ARM_OP_GROUP_MveAddrModeRQOperand, shift), \ OpNum, shift); \ MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ @@ -514,7 +514,7 @@ DEFINE_printMveAddrModeRQOperand(2); static inline void CONCAT(printAddrMode5Operand, AlwaysPrintImm0)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, \ + add_cs_detail_1(MI, \ CONCAT(ARM_OP_GROUP_AddrMode5Operand, \ AlwaysPrintImm0), \ OpNum, AlwaysPrintImm0); \ @@ -543,7 +543,7 @@ DEFINE_printAddrMode5Operand(true); static inline void CONCAT(printAddrMode5FP16Operand, AlwaysPrintImm0)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, \ + add_cs_detail_1(MI, \ CONCAT(ARM_OP_GROUP_AddrMode5FP16Operand, \ AlwaysPrintImm0), \ OpNum, AlwaysPrintImm0); \ @@ -911,7 +911,7 @@ static inline void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) static inline void CONCAT(printAdrLabelOperand, scale)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ + add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ OpNum, scale); \ MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \ \ @@ -1078,7 +1078,7 @@ static inline void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void CONCAT(printAddrModeImm12Operand, AlwaysPrintImm0)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, \ + add_cs_detail_1(MI, \ CONCAT(ARM_OP_GROUP_AddrModeImm12Operand, \ AlwaysPrintImm0), \ OpNum, AlwaysPrintImm0); \ @@ -1119,7 +1119,7 @@ DEFINE_printAddrModeImm12Operand(true); AlwaysPrintImm0)(MCInst * MI, \ unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, \ + add_cs_detail_1(MI, \ CONCAT(ARM_OP_GROUP_T2AddrModeImm8Operand, \ AlwaysPrintImm0), \ OpNum, AlwaysPrintImm0); \ @@ -1155,7 +1155,7 @@ DEFINE_printT2AddrModeImm8Operand(false); AlwaysPrintImm0)(MCInst * MI, \ unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, \ + add_cs_detail_1(MI, \ CONCAT(ARM_OP_GROUP_T2AddrModeImm8s4Operand, \ AlwaysPrintImm0), \ OpNum, AlwaysPrintImm0); \ @@ -1599,7 +1599,7 @@ static inline void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, static inline void CONCAT(printMVEVectorList, NumRegs)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ + add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ OpNum, NumRegs); \ unsigned Reg = \ MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ @@ -1620,7 +1620,7 @@ DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) CONCAT(Angle, Remainder))( \ MCInst * MI, unsigned OpNo, SStream *O) \ { \ - add_cs_detail( \ + add_cs_detail_2( \ MI, \ CONCAT(CONCAT(ARM_OP_GROUP_ComplexRotationOp, Angle), \ Remainder), \ diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 7332efe06c..8be80e0852 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -1967,14 +1967,14 @@ static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group, /// Calls to this function are should not be added by hand! Please checkout the /// patch `AddCSDetail` of the CppTranslator. void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, - va_list args) + size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) { if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) return; switch (op_group) { case ARM_OP_GROUP_RegImmShift: { - ARM_AM_ShiftOpc shift_opc = va_arg(args, ARM_AM_ShiftOpc); - unsigned shift_imm = va_arg(args, unsigned); + ARM_AM_ShiftOpc shift_opc = (ARM_AM_ShiftOpc)templ_arg_0; + unsigned shift_imm = templ_arg_1; add_cs_detail_RegImmShift(MI, shift_opc, shift_imm); return; } @@ -1997,22 +1997,16 @@ void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, case ARM_OP_GROUP_MveAddrModeRQOperand_3: case ARM_OP_GROUP_MveAddrModeRQOperand_1: case ARM_OP_GROUP_MveAddrModeRQOperand_2: { - unsigned op_num = va_arg(args, unsigned); - uint64_t templ_arg_0 = va_arg(args, uint64_t); add_cs_detail_template_1(MI, op_group, op_num, templ_arg_0); return; } case ARM_OP_GROUP_ComplexRotationOp_180_90: case ARM_OP_GROUP_ComplexRotationOp_90_0: { - unsigned op_num = va_arg(args, unsigned); - uint64_t templ_arg_0 = va_arg(args, uint64_t); - uint64_t templ_arg_1 = va_arg(args, uint64_t); add_cs_detail_template_2(MI, op_group, op_num, templ_arg_0, templ_arg_1); return; } } - unsigned op_num = va_arg(args, unsigned); add_cs_detail_general(MI, op_group, op_num); } diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index 8ec0350310..bb547a4f8c 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -6,6 +6,7 @@ #include "../../include/capstone/capstone.h" #include "../../utils.h" +#include "../../Mapping.h" #include "ARMBaseInfo.h" typedef enum { @@ -51,16 +52,29 @@ void ARM_init_mri(MCRegisterInfo *MRI); // cs_detail related functions void ARM_init_cs_detail(MCInst *MI); void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, - va_list args); + size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1); static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, - ...) + size_t op_num) { - if (!MI->flat_insn->detail) + if (!detail_is_set(MI)) return; - va_list args; - va_start(args, op_group); - ARM_add_cs_detail(MI, op_group, args); - va_end(args); + ARM_add_cs_detail(MI, op_group, op_num, 0, 0); +} + +static inline void add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num, uint64_t templ_arg_0) +{ + if (!detail_is_set(MI)) + return; + ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, 0); +} + +static inline void add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) +{ + if (!detail_is_set(MI)) + return; + ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, templ_arg_1); } void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, diff --git a/arch/LoongArch/LoongArchMapping.c b/arch/LoongArch/LoongArchMapping.c index a7d3d5f442..17ba2b6e70 100644 --- a/arch/LoongArch/LoongArchMapping.c +++ b/arch/LoongArch/LoongArchMapping.c @@ -537,12 +537,11 @@ void LoongArch_set_detail_op_reg(MCInst *MI, unsigned OpNum, loongarch_reg Reg) } void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group, - va_list args) + size_t OpNum) { if (!detail_is_set(MI)) return; - unsigned OpNum = va_arg(args, unsigned); // Handle memory operands later cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM; diff --git a/arch/LoongArch/LoongArchMapping.h b/arch/LoongArch/LoongArchMapping.h index 42dc9bd4ad..986ed84530 100644 --- a/arch/LoongArch/LoongArchMapping.h +++ b/arch/LoongArch/LoongArchMapping.h @@ -39,16 +39,13 @@ bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len, // cs_detail related functions void LoongArch_init_cs_detail(MCInst *MI); void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group, - va_list args); + size_t op_num); static inline void add_cs_detail(MCInst *MI, - int /* loongarch_op_group */ op_group, ...) + int /* loongarch_op_group */ op_group, size_t op_num) { - if (!MI->flat_insn->detail) + if (!detail_is_set(MI)) return; - va_list args; - va_start(args, op_group); - LoongArch_add_cs_detail(MI, op_group, args); - va_end(args); + LoongArch_add_cs_detail(MI, op_group, op_num); } #endif // CS_LOONGARCH_MAPPING_H diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index 8ad5936dc3..9d096a6a8a 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -411,13 +411,11 @@ static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum) Mips_set_detail_op_imm(MI, OpNum, Target); } -void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args) +void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, size_t OpNum) { if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) return; - unsigned OpNum = va_arg(args, unsigned); - switch (op_group) { default: printf("Operand group %d not handled!\n", op_group); diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h index 89980848ef..97f403d3fa 100644 --- a/arch/Mips/MipsMapping.h +++ b/arch/Mips/MipsMapping.h @@ -39,16 +39,13 @@ void Mips_init_cs_detail(MCInst *MI); void Mips_set_mem_access(MCInst *MI, bool status); -void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args); +void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, size_t op_num); -static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, ...) +static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, size_t op_num) { if (!detail_is_set(MI)) return; - va_list args; - va_start(args, op_group); - Mips_add_cs_detail(MI, op_group, args); - va_end(args); + Mips_add_cs_detail(MI, op_group, op_num); } static inline void set_mem_access(MCInst *MI, bool status) diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c index c06ff9369e..78bdf48936 100644 --- a/arch/SystemZ/SystemZMapping.c +++ b/arch/SystemZ/SystemZMapping.c @@ -159,15 +159,13 @@ const char *SystemZ_group_name(csh handle, unsigned int id) #endif } -void SystemZ_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group, - va_list args) +void SystemZ_add_cs_detail(MCInst *MI, int /* systemz_op_group */ op_group, + size_t op_num) { #ifndef CAPSTONE_DIET if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) return; - unsigned op_num = va_arg(args, unsigned); - switch (op_group) { default: printf("Operand group %d not handled\n", op_group); diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 965f616831..230a599e71 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -6,6 +6,7 @@ #include +#include "../../Mapping.h" #include "../../cs_priv.h" typedef enum { @@ -36,17 +37,14 @@ void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am); void SystemZ_add_cs_detail(MCInst *MI, int /* systemz_op_group */ op_group, - va_list args); + size_t op_num); static inline void add_cs_detail(MCInst *MI, - int /* aarch64_op_group */ op_group, ...) + int /* systemz_op_group */ op_group, size_t op_num) { - if (!MI->flat_insn->detail) + if (!detail_is_set(MI)) return; - va_list args; - va_start(args, op_group); - SystemZ_add_cs_detail(MI, op_group, args); - va_end(args); + SystemZ_add_cs_detail(MI, op_group, op_num); } #endif // CS_SYSTEMZ_MAP_H From 6c50d4861cebac7978f8aabaf28b2dd5795bcd41 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 10 Feb 2026 01:00:54 +0100 Subject: [PATCH 09/16] Install missing libc for ARM --- .github/workflows/CrossBuilds.yml | 2 +- cross_configs/linux_arm_ubuntu24.cmake | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.github/workflows/CrossBuilds.yml b/.github/workflows/CrossBuilds.yml index 696bd707b9..77d5942791 100644 --- a/.github/workflows/CrossBuilds.yml +++ b/.github/workflows/CrossBuilds.yml @@ -88,7 +88,7 @@ jobs: diet-build: 'OFF', build_type: 'Debug', diet_build: false, - packages: 'gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static', + packages: 'gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-armhf-cross libc6-dev-armhf-cross qemu-user-static', cross_file: 'cross_configs/linux_arm_ubuntu24.cmake', } - { diff --git a/cross_configs/linux_arm_ubuntu24.cmake b/cross_configs/linux_arm_ubuntu24.cmake index 042758ca67..349a8b6587 100644 --- a/cross_configs/linux_arm_ubuntu24.cmake +++ b/cross_configs/linux_arm_ubuntu24.cmake @@ -1,5 +1,5 @@ # This example file is for builds on Ubunutu 24.04. -# sudo apt install gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-dev-armhf-cross qemu-user-static +# sudo apt install gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-armhf-cross libc6-dev-armhf-cross qemu-user-static set(CMAKE_SYSTEM_NAME Linux) set(CMAKE_SYSTEM_PROCESSOR arm) @@ -7,11 +7,11 @@ set(CMAKE_C_COMPILER arm-linux-gnueabihf-gcc) set(CMAKE_ASM_COMPILER arm-linux-gnueabihf-gcc) set(CMAKE_CROSS_COMPILING 1) -set(CMAKE_SYSROOT /usr/arm-linux-gnueabihf) +set(CMAKE_SYSROOT /usr/arm-linux-gnueabihf/usr) set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY) -set(CMAKE_CROSSCOMPILING_EMULATOR qemu-arm-static;-L;${CMAKE_SYSROOT}) +set(CMAKE_CROSSCOMPILING_EMULATOR qemu-arm-static;-L;/usr/arm-linux-gnueabihf) From c7b12ff8d048cc98dee864d73ecd6962e790b013 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 10 Feb 2026 01:31:20 +0100 Subject: [PATCH 10/16] Replace strndup with own implementation for Windows. --- suite/cstest/include/helper.h | 1 + suite/cstest/src/helper.c | 20 ++++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/suite/cstest/include/helper.h b/suite/cstest/include/helper.h index b9b89773f6..80529431bc 100644 --- a/suite/cstest/include/helper.h +++ b/suite/cstest/include/helper.h @@ -17,5 +17,6 @@ void replace_hex(char *src, size_t src_len); void replace_negative(char *src, size_t src_len, size_t arch_bits); void norm_spaces(char *str); void str_to_lower(char *str); +char *cs_strndup(const char *s, size_t n); #endif /* HELPER_H */ diff --git a/suite/cstest/src/helper.c b/suite/cstest/src/helper.c index 313973506f..b22a2a94ee 100644 --- a/suite/cstest/src/helper.c +++ b/suite/cstest/src/helper.c @@ -12,6 +12,22 @@ #include "cmocka.h" #include "helper.h" +char *cs_strndup(const char *s, size_t n) { + if (!s) { + return NULL; + } + size_t l = strnlen(s, n); + if (l == SIZE_MAX) { + return NULL; + } + char *out = calloc(sizeof(char), l + 1); + if (!out) { + return NULL; + } + memcpy(out, s, l); + return out; +} + void add_str(char **src, const char *format, ...) { char *tmp; @@ -49,7 +65,7 @@ void replace_hex(char *src, size_t src_len) value = 0; valid = 0; - tmp_tmp = strndup(tmp, orig_found - tmp); + tmp_tmp = cs_strndup(tmp, orig_found - tmp); while (*found != '\0' && isxdigit(*found)) { valid = 1; if (*found >= 'a' && *found <= 'f') @@ -114,7 +130,7 @@ void replace_negative(char *src, size_t src_len, size_t arch_bits) found++; } - tmp_tmp = strndup(tmp, orig_found - tmp); + tmp_tmp = cs_strndup(tmp, orig_found - tmp); if (valid == 1) { *orig_found = '\0'; if (arch_bits == 16) { From fd586a85ba96c45c4d46c4490d9a6f6a1d16eb80 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 10 Feb 2026 02:04:19 +0100 Subject: [PATCH 11/16] Fix broken number formatting. --- arch/M68K/M68KInstPrinter.c | 50 ++++++++++++++++++------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c index 5aa4c8dd06..38c3fdff2e 100644 --- a/arch/M68K/M68KInstPrinter.c +++ b/arch/M68K/M68KInstPrinter.c @@ -124,11 +124,11 @@ static void printRegbitsRange(char *buffer, size_t buf_len, uint32_t data, if (buffer[0] != 0) strncat(buffer, "/", buf_len - 1); - snprintf(buffer + strlen(buffer), buf_len, "%s%d", + snprintf(buffer + strlen(buffer), buf_len, "%s%" PRId32, prefix, first); if (run_length > 0) snprintf(buffer + strlen(buffer), buf_len, - "-%s%d", prefix, first + run_length); + "-%s%" PRId32, prefix, first + run_length); } } } @@ -179,33 +179,33 @@ static void printAddressingMode(SStream *O, unsigned int pc, break; case M68K_AM_REG_DIRECT_DATA: - SStream_concat(O, "d%d", (op->reg - M68K_REG_D0)); + SStream_concat(O, "d%" PRId32, (op->reg - M68K_REG_D0)); break; case M68K_AM_REG_DIRECT_ADDR: - SStream_concat(O, "a%d", (op->reg - M68K_REG_A0)); + SStream_concat(O, "a%" PRId32, (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR: - SStream_concat(O, "(a%d)", (op->reg - M68K_REG_A0)); + SStream_concat(O, "(a%" PRId32 ")", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_POST_INC: - SStream_concat(O, "(a%d)+", (op->reg - M68K_REG_A0)); + SStream_concat(O, "(a%" PRId32 ")+", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_PRE_DEC: - SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); + SStream_concat(O, "-(a%" PRId32 ")", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_DISP: - SStream_concat(O, "%s$%x(a%d)", op->mem.disp < 0 ? "-" : "", + SStream_concat(O, "%s$%" PRIx16 "(a%" PRId32 ")", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); break; case M68K_AM_PCI_DISP: - SStream_concat(O, "$%x(pc)", pc + 2 + op->mem.disp); + SStream_concat(O, "$%" PRIx32 "(pc)", pc + 2 + op->mem.disp); break; case M68K_AM_ABSOLUTE_DATA_SHORT: - SStream_concat(O, "$%x.w", op->imm); + SStream_concat(O, "$%" PRIx32 ".w", op->imm); break; case M68K_AM_ABSOLUTE_DATA_LONG: - SStream_concat(O, "$%x.l", op->imm); + SStream_concat(O, "$%" PRIx64 ".l", op->imm); break; case M68K_AM_IMMEDIATE: if (inst->op_size.type == M68K_SIZE_TYPE_FPU) { @@ -223,15 +223,15 @@ static void printAddressingMode(SStream *O, unsigned int pc, break; #endif } - SStream_concat(O, "#$%x", op->imm); + SStream_concat(O, "#$%" PRIx64, op->imm); break; case M68K_AM_PCI_INDEX_8_BIT_DISP: - SStream_concat(O, "$%x(pc,%s%s.%c)", pc + 2 + op->mem.disp, + SStream_concat(O, "$%" PRIx32 "(pc,%s%s.%c)", pc + 2 + op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); break; case M68K_AM_AREGI_INDEX_8_BIT_DISP: - SStream_concat(O, "%s$%x(%s,%s%s.%c)", + SStream_concat(O, "%s$%" PRIx16 "(%s,%s%s.%c)", op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), @@ -241,9 +241,9 @@ static void printAddressingMode(SStream *O, unsigned int pc, case M68K_AM_AREGI_INDEX_BASE_DISP: if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { - SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp); + SStream_concat(O, "$%" PRIx32, pc + 2 + op->mem.in_disp); } else if (op->mem.in_disp != 0) { - SStream_concat(O, "%s$%x", + SStream_concat(O, "%s$%" PRIx32, op->mem.in_disp >= 0 ? "" : "-", abs(op->mem.in_disp)); } @@ -253,7 +253,7 @@ static void printAddressingMode(SStream *O, unsigned int pc, if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { SStream_concat0(O, "pc"); } else if (op->mem.base_reg != M68K_REG_INVALID) { - SStream_concat(O, "a%d", + SStream_concat(O, "a%" PRId32, op->mem.base_reg - M68K_REG_A0); } @@ -267,7 +267,7 @@ static void printAddressingMode(SStream *O, unsigned int pc, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); if (op->mem.scale > 0) - SStream_concat(O, "%s*%s%d", s_spacing, + SStream_concat(O, "%s*%s%" PRId8, s_spacing, s_spacing, op->mem.scale); } @@ -284,9 +284,9 @@ static void printAddressingMode(SStream *O, unsigned int pc, if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) { - SStream_concat(O, "$%x", pc + 2 + op->mem.in_disp); + SStream_concat(O, "$%" PRIx32, pc + 2 + op->mem.in_disp); } else if (op->mem.in_disp != 0) { - SStream_concat(O, "%s$%x", + SStream_concat(O, "%s$%" PRIx32, op->mem.in_disp >= 0 ? "" : "-", abs(op->mem.in_disp)); } @@ -310,7 +310,7 @@ static void printAddressingMode(SStream *O, unsigned int pc, op->mem.index_size ? 'l' : 'w'); if (op->mem.scale > 0) - SStream_concat(O, "%s*%s%d", s_spacing, s_spacing, + SStream_concat(O, "%s*%s%" PRId8, s_spacing, s_spacing, op->mem.scale); if (op->address_mode == M68K_AM_MEMI_PRE_INDEX || @@ -318,7 +318,7 @@ static void printAddressingMode(SStream *O, unsigned int pc, SStream_concat0(O, "]"); if (op->mem.out_disp != 0) { - SStream_concat(O, ",%s%s$%x", s_spacing, + SStream_concat(O, ",%s%s$%" PRIx32, s_spacing, op->mem.out_disp >= 0 ? "" : "-", abs(op->mem.out_disp)); } @@ -326,13 +326,13 @@ static void printAddressingMode(SStream *O, unsigned int pc, SStream_concat0(O, ")"); break; case M68K_AM_BRANCH_DISPLACEMENT: - SStream_concat(O, "$%x", pc + 2 + op->br_disp.disp); + SStream_concat(O, "$%" PRIx32, pc + 2 + op->br_disp.disp); default: break; } if (op->mem.bitfield) - SStream_concat(O, "{%d:%d}", op->mem.offset, op->mem.width); + SStream_concat(O, "{%" PRId8 ":%" PRId8 "}", op->mem.offset, op->mem.width); } #endif @@ -374,7 +374,7 @@ void M68K_printInst(MCInst *MI, SStream *O, void *PrinterInfo) if (MI->Opcode == M68K_INS_INVALID) { if (ext->op_count) - SStream_concat(O, "dc.w $%x", ext->operands[0].imm); + SStream_concat(O, "dc.w $%" PRIx32, ext->operands[0].imm); else SStream_concat(O, "dc.w $"); return; From 30ec1b2964e2f834950296fb832c89ba32b2df98 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 10 Feb 2026 02:44:41 +0100 Subject: [PATCH 12/16] Fix formatting of error message with instruction bytes. --- suite/cstest/src/test_case.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/suite/cstest/src/test_case.c b/suite/cstest/src/test_case.c index 54d71e45ef..537b9b9423 100644 --- a/suite/cstest/src/test_case.c +++ b/suite/cstest/src/test_case.c @@ -218,11 +218,11 @@ static void _print_insn(csh *handle, cs_insn *insn) { cm_print_error("Failed instruction: %s %s", insn->mnemonic, insn->op_str); - cm_print_error("(0x%x", insn->bytes[0]); + cm_print_error(" <=> \"0x%x", insn->bytes[0]); for (int i = 1; i < insn->size; i++) { - cm_print_error(", 0x%x", insn->bytes[i]); + cm_print_error(", 0x%02x", insn->bytes[i]); } - cm_print_error("%s", ")\n"); + cm_print_error("%s", "\"\n"); } /// Compares the decoded instructions @insns against the @expected values and returns the result. From 39e5f1d6213998ed6b841cffd4a6cbad51e8f690 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Tue, 10 Feb 2026 02:48:41 +0100 Subject: [PATCH 13/16] Fix string formatting issues with 32bit systems. --- arch/MOS65XX/MOS65XXDisassembler.c | 77 ++++++++++++++++-------------- 1 file changed, 41 insertions(+), 36 deletions(-) diff --git a/arch/MOS65XX/MOS65XXDisassembler.c b/arch/MOS65XX/MOS65XXDisassembler.c index c2b1119d7b..8cd9403bf0 100644 --- a/arch/MOS65XX/MOS65XXDisassembler.c +++ b/arch/MOS65XX/MOS65XXDisassembler.c @@ -285,7 +285,7 @@ void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) case MOS65XX_INS_BBS: case MOS65XX_INS_RMB: case MOS65XX_INS_SMB: - SStream_concat(O, "%d", (opcode >> 4) & 0x07); + SStream_concat(O, "%" PRId8, (opcode >> 4) & 0x07); break; default: break; @@ -306,111 +306,116 @@ void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo) case MOS65XX_AM_IMM: if (MI->imm_size == 1) - SStream_concat(O, " #%s%02x", prefix, value); + SStream_concat(O, " #%s%02" PRIx32, prefix, value); else - SStream_concat(O, " #%s%04x", prefix, value); + SStream_concat(O, " #%s%04" PRIx32, prefix, value); break; case MOS65XX_AM_ZP: - SStream_concat(O, " %s%02x", prefix, value); + SStream_concat(O, " %s%02" PRIx32, prefix, value); break; case MOS65XX_AM_ABS: - SStream_concat(O, " %s%04x", prefix, value); + SStream_concat(O, " %s%04" PRIx32, prefix, value); break; case MOS65XX_AM_ABS_LONG_X: - SStream_concat(O, " %s%06x, x", prefix, value); + SStream_concat(O, " %s%06" PRIx32 ", x", prefix, value); break; case MOS65XX_AM_INT: - SStream_concat(O, " %s%02x", prefix, value); + SStream_concat(O, " %s%02" PRIx32, prefix, value); break; case MOS65XX_AM_ABS_X: - SStream_concat(O, " %s%04x, x", prefix, value); + SStream_concat(O, " %s%04" PRIx32 ", x", prefix, value); break; case MOS65XX_AM_ABS_Y: - SStream_concat(O, " %s%04x, y", prefix, value); + SStream_concat(O, " %s%04" PRIx32 ", y", prefix, value); break; case MOS65XX_AM_ABS_LONG: - SStream_concat(O, " %s%06x", prefix, value); + SStream_concat(O, " %s%06" PRIx32, prefix, value); break; case MOS65XX_AM_ZP_X: - SStream_concat(O, " %s%02x, x", prefix, value); + SStream_concat(O, " %s%02" PRIx32 ", x", prefix, value); break; case MOS65XX_AM_ZP_Y: - SStream_concat(O, " %s%02x, y", prefix, value); + SStream_concat(O, " %s%02" PRIx32 ", y", prefix, value); break; - case MOS65XX_AM_REL: + case MOS65XX_AM_REL: { if (MI->op1_size == 1) - value = 2 + (signed char)value; + value = 2 + (int8_t)value; else - value = 3 + (signed short)value; + value = 3 + (int16_t)value; - SStream_concat(O, " %s%04x", prefix, - (MI->address + value) & 0xffff); - break; + uint32_t addr = MI->address; + SStream_concat(O, " %s%04" PRIx16, prefix, + (addr + value) & 0xffff); + break; + } case MOS65XX_AM_ABS_IND: - SStream_concat(O, " (%s%04x)", prefix, value); + SStream_concat(O, " (%s%04" PRIx32 ")", prefix, value); break; case MOS65XX_AM_ABS_X_IND: - SStream_concat(O, " (%s%04x, x)", prefix, value); + SStream_concat(O, " (%s%04" PRIx32 ", x)", prefix, value); break; case MOS65XX_AM_ABS_IND_LONG: - SStream_concat(O, " [%s%04x]", prefix, value); + SStream_concat(O, " [%s%04" PRIx32 "]", prefix, value); break; case MOS65XX_AM_ZP_IND: - SStream_concat(O, " (%s%02x)", prefix, value); + SStream_concat(O, " (%s%02" PRIx32 ")", prefix, value); break; case MOS65XX_AM_ZP_X_IND: - SStream_concat(O, " (%s%02x, x)", prefix, value); + SStream_concat(O, " (%s%02" PRIx32 ", x)", prefix, value); break; case MOS65XX_AM_ZP_IND_Y: - SStream_concat(O, " (%s%02x), y", prefix, value); + SStream_concat(O, " (%s%02" PRIx32 "), y", prefix, value); break; case MOS65XX_AM_ZP_IND_LONG: - SStream_concat(O, " [%s%02x]", prefix, value); + SStream_concat(O, " [%s%02" PRIx32 "]", prefix, value); break; case MOS65XX_AM_ZP_IND_LONG_Y: - SStream_concat(O, " [%s%02x], y", prefix, value); + SStream_concat(O, " [%s%02" PRIx32 "], y", prefix, value); break; case MOS65XX_AM_SR: - SStream_concat(O, " %s%02x, s", prefix, value); + SStream_concat(O, " %s%02" PRIx32 ", s", prefix, value); break; case MOS65XX_AM_SR_IND_Y: - SStream_concat(O, " (%s%02x, s), y", prefix, value); + SStream_concat(O, " (%s%02" PRIx32 ", s), y", prefix, value); break; case MOS65XX_AM_BLOCK: - SStream_concat(O, " %s%02x, %s%02x", prefix, - MI->Operands[0].ImmVal, prefix, - MI->Operands[1].ImmVal); + SStream_concat(O, " %s%02" PRIx32 ", %s%02" PRIx32, prefix, + (uint32_t)MI->Operands[0].ImmVal, prefix, + (uint32_t)MI->Operands[1].ImmVal); break; - case MOS65XX_AM_ZP_REL: - value = 3 + (signed char)MI->Operands[1].ImmVal; + case MOS65XX_AM_ZP_REL: { + value = 3 + (int8_t)MI->Operands[1].ImmVal; + uint32_t addr = MI->address; + uint32_t target = (addr + value) & 0xffff; /* BBR0, zp, rel and BBS0, zp, rel */ - SStream_concat(O, " %s%02x, %s%04x", prefix, - MI->Operands[0].ImmVal, prefix, - (MI->address + value) & 0xffff); + SStream_concat(O, " %s%02" PRIx32 ", %s%04" PRIx32, prefix, + (uint32_t)MI->Operands[0].ImmVal, prefix, + target); break; } + } #endif } From 02a50cbdad3f1ff5155d9c97b9f3e0b3f1276a41 Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 13 Feb 2026 15:00:11 +0100 Subject: [PATCH 14/16] Replace all add_cs_detail() functions with the arch specific ones. --- arch/ARC/ARCInstPrinter.c | 14 +- arch/ARC/ARCMapping.c | 2 +- arch/ARC/ARCMapping.h | 9 +- arch/ARM/ARMInstPrinter.c | 174 +++++++++--------- arch/ARM/ARMMapping.c | 20 +- arch/ARM/ARMMapping.h | 29 +-- arch/LoongArch/LoongArchInstPrinter.c | 4 +- arch/LoongArch/LoongArchMapping.c | 2 +- arch/LoongArch/LoongArchMapping.h | 9 +- arch/Mips/MipsInstPrinter.c | 24 +-- arch/Mips/MipsMapping.c | 2 +- arch/Mips/MipsMapping.h | 9 +- arch/SystemZ/SystemZInstPrinter.c | 40 ++-- arch/SystemZ/SystemZMapping.c | 2 +- arch/SystemZ/SystemZMapping.h | 10 +- .../cpptranslator/patches/AddCSDetail.py | 2 +- 16 files changed, 161 insertions(+), 191 deletions(-) diff --git a/arch/ARC/ARCInstPrinter.c b/arch/ARC/ARCInstPrinter.c index c7f991b8c5..e4e35132be 100644 --- a/arch/ARC/ARCInstPrinter.c +++ b/arch/ARC/ARCInstPrinter.c @@ -124,7 +124,7 @@ static void printInst(MCInst *MI, uint64_t Address, const char *Annot, static void printOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARC_OP_GROUP_Operand, OpNum); + ARC_add_cs_detail_0(MI, ARC_OP_GROUP_Operand, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isReg(Op)) { printRegName(O, MCOperand_getReg(Op)); @@ -143,7 +143,7 @@ static void printOperandAddr(MCInst *MI, uint64_t Address, unsigned OpNum, static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARC_OP_GROUP_MemOperandRI, OpNum); + ARC_add_cs_detail_0(MI, ARC_OP_GROUP_MemOperandRI, OpNum); MCOperand *base = MCInst_getOperand(MI, (OpNum)); MCOperand *offset = MCInst_getOperand(MI, (OpNum + 1)); CS_ASSERT((MCOperand_isReg(base) && "Base should be register.")); @@ -155,7 +155,7 @@ static void printMemOperandRI(MCInst *MI, unsigned OpNum, SStream *O) static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARC_OP_GROUP_PredicateOperand, OpNum); + ARC_add_cs_detail_0(MI, ARC_OP_GROUP_PredicateOperand, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate.")); @@ -165,7 +165,7 @@ static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum); + ARC_add_cs_detail_0(MI, ARC_OP_GROUP_BRCCPredicateOperand, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); CS_ASSERT((MCOperand_isImm(Op) && "Predicate operand is immediate.")); SStream_concat0(O, ARCBRCondCodeToString( @@ -174,7 +174,7 @@ static void printBRCCPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) static void printCCOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, ARC_OP_GROUP_CCOperand, OpNum); + ARC_add_cs_detail_0(MI, ARC_OP_GROUP_CCOperand, OpNum); SStream_concat0(O, ARCCondCodeToString((ARCCC_CondCode)MCOperand_getImm( MCInst_getOperand(MI, (OpNum))))); } @@ -195,7 +195,7 @@ static void printU6ShiftedBy(unsigned ShiftBy, MCInst *MI, int OpNum, static void printU6(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, ARC_OP_GROUP_U6, OpNum); + ARC_add_cs_detail_0(MI, ARC_OP_GROUP_U6, OpNum); printU6ShiftedBy(0, MI, OpNum, O); } @@ -210,4 +210,4 @@ const char *ARC_LLVM_getRegisterName(unsigned RegNo) return getRegisterName(RegNo); } -#endif \ No newline at end of file +#endif diff --git a/arch/ARC/ARCMapping.c b/arch/ARC/ARCMapping.c index 3e84743153..798b46b05d 100644 --- a/arch/ARC/ARCMapping.c +++ b/arch/ARC/ARCMapping.c @@ -209,7 +209,7 @@ void ARC_set_detail_op_reg(MCInst *MI, unsigned OpNum, arc_reg Reg) ARC_inc_op_count(MI); } -void ARC_add_cs_detail(MCInst *MI, int op_group, size_t OpNum) +void ARC_add_cs_detail_0(MCInst *MI, int op_group, size_t OpNum) { if (!detail_is_set(MI)) return; diff --git a/arch/ARC/ARCMapping.h b/arch/ARC/ARCMapping.h index 6794554c03..25fff8cebe 100644 --- a/arch/ARC/ARCMapping.h +++ b/arch/ARC/ARCMapping.h @@ -38,14 +38,7 @@ bool ARC_getInstruction(csh handle, const uint8_t *code, size_t code_len, void ARC_init_cs_detail(MCInst *MI); void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum, arc_op_type ImmType, int64_t Imm); -void ARC_add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group, +void ARC_add_cs_detail_0(MCInst *MI, int /* arc_op_group */ op_group, size_t op_num); -static inline void add_cs_detail(MCInst *MI, int /* arc_op_group */ op_group, - size_t op_num) -{ - if (!detail_is_set(MI)) - return; - ARC_add_cs_detail(MI, op_group, op_num); -} #endif diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index e4448effac..ffe0f40c03 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -76,7 +76,7 @@ static inline void printRegImmShift(MCInst *MI, SStream *O, ARM_AM_ShiftOpc ShOpc, unsigned ShImm, bool UseMarkup) { - add_cs_detail_2(MI, ARM_OP_GROUP_RegImmShift, -1, ShOpc, ShImm); + ARM_add_cs_detail_2(MI, ARM_OP_GROUP_RegImmShift, -1, ShOpc, ShImm); if (ShOpc == ARM_AM_no_shift || (ShOpc == ARM_AM_lsl && !ShImm)) return; SStream_concat0(O, ", "); @@ -96,7 +96,7 @@ static inline void printRegImmShift(MCInst *MI, SStream *O, static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_PredicateOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_PredicateOperand, OpNum); ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( MCInst_getOperand(MI, (OpNum))); // Handle the undefined 15 CC value here for printing so we don't abort(). @@ -115,7 +115,7 @@ static void printRegName(SStream *OS, unsigned RegNo) static inline void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_Operand, OpNo); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_Operand, OpNo); MCOperand *Op = MCInst_getOperand(MI, (OpNo)); if (MCOperand_isReg(Op)) { unsigned Reg = MCOperand_getReg(Op); @@ -132,7 +132,7 @@ static inline void printOperand(MCInst *MI, unsigned OpNo, SStream *O) static inline void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_RegisterList, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_RegisterList, OpNum); if (MCInst_getOpcode(MI) != ARM_t2CLRM) { } @@ -148,7 +148,7 @@ static inline void printRegisterList(MCInst *MI, unsigned OpNum, SStream *O) static inline void printSBitModifierOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_SBitModifierOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_SBitModifierOperand, OpNum); if (MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))) { SStream_concat0(O, "s"); } @@ -187,7 +187,7 @@ static inline void printOperandAddr(MCInst *MI, uint64_t Address, static inline void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_ThumbLdrLabelOperand, OpNum); MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isExpr(MO1)) { // MO1.getExpr()->print(O, &MAI); @@ -216,7 +216,7 @@ static inline void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNum, // REG 0 IMM,SH_OPC - e.g. R5, LSL #3 static inline void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_SORegRegOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_SORegRegOperand, OpNum); MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); MCOperand *MO3 = MCInst_getOperand(MI, (OpNum + 2)); @@ -237,7 +237,7 @@ static inline void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_SORegImmOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_SORegImmOperand, OpNum); MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); @@ -293,7 +293,7 @@ static inline void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned Op, static inline void printAddrModeTBB(MCInst *MI, unsigned Op, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_AddrModeTBB, Op); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_AddrModeTBB, Op); MCOperand *MO1 = MCInst_getOperand(MI, (Op)); MCOperand *MO2 = MCInst_getOperand(MI, (Op + 1)); SStream_concat(O, "%s", markup("csh->mode, @@ -644,21 +644,21 @@ static inline void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) static inline void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_InstSyncBOption, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_InstSyncBOption, OpNum); unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); SStream_concat0(O, ARM_ISB_InstSyncBOptToString(val)); } static inline void printTraceSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_TraceSyncBOption, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_TraceSyncBOption, OpNum); unsigned val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); SStream_concat0(O, ARM_TSB_TraceSyncBOptToString(val)); } static inline void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_ShiftImmOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_ShiftImmOperand, OpNum); unsigned ShiftOp = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); bool isASR = (ShiftOp & (1 << 5)) != 0; unsigned Amt = ShiftOp & 0x1f; @@ -675,7 +675,7 @@ static inline void printShiftImmOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_PKHLSLShiftImm, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_PKHLSLShiftImm, OpNum); unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); if (Imm == 0) return; @@ -687,7 +687,7 @@ static inline void printPKHLSLShiftImm(MCInst *MI, unsigned OpNum, SStream *O) static inline void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_PKHASRShiftImm, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_PKHASRShiftImm, OpNum); unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); // A shift amount of 32 is encoded as 0. if (Imm == 0) @@ -700,7 +700,7 @@ static inline void printPKHASRShiftImm(MCInst *MI, unsigned OpNum, SStream *O) static inline void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_GPRPairOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_GPRPairOperand, OpNum); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); printRegName(O, MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_gsub_0)); SStream_concat0(O, ", "); @@ -709,7 +709,7 @@ static inline void printGPRPairOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_SetendOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_SetendOperand, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); if (MCOperand_getImm(Op)) SStream_concat0(O, "be"); @@ -719,14 +719,14 @@ static inline void printSetendOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printCPSIMod(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_CPSIMod, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_CPSIMod, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); SStream_concat0(O, ARM_PROC_IModToString(MCOperand_getImm(Op))); } static inline void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_CPSIFlag, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_CPSIFlag, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); unsigned IFlags = MCOperand_getImm(Op); for (int i = 2; i >= 0; --i) @@ -739,7 +739,7 @@ static inline void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O) static inline void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_MSRMaskOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MSRMaskOperand, OpNum); MCOperand *Op = MCInst_getOperand(MI, (OpNum)); if (ARM_getFeatureBits(MI->csh->mode, ARM_FeatureMClass)) { @@ -833,7 +833,7 @@ static inline void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_BankedRegOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_BankedRegOperand, OpNum); uint32_t Banked = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); const ARMBankedReg_BankedReg *TheReg = ARMBankedReg_lookupBankedRegByEncoding(Banked); @@ -849,7 +849,7 @@ static inline void printBankedRegOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_MandatoryPredicateOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MandatoryPredicateOperand, OpNum); ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( MCInst_getOperand(MI, (OpNum))); SStream_concat0(O, ARMCondCodeToString(CC)); @@ -858,7 +858,7 @@ static inline void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, static inline void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_MandatoryRestrictedPredicateOperand, + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MandatoryRestrictedPredicateOperand, OpNum); if ((ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) == ARMCC_HS) @@ -870,7 +870,7 @@ printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_MandatoryInvertedPredicateOperand, + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MandatoryInvertedPredicateOperand, OpNum); ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( MCInst_getOperand(MI, (OpNum))); @@ -879,13 +879,13 @@ printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) static inline void printNoHashImmediate(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_NoHashImmediate, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_NoHashImmediate, OpNum); printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); } static inline void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_PImmediate, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_PImmediate, OpNum); SStream_concat( O, "%s%" PRIu32, "p", (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); @@ -893,7 +893,7 @@ static inline void printPImmediate(MCInst *MI, unsigned OpNum, SStream *O) static inline void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_CImmediate, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_CImmediate, OpNum); SStream_concat( O, "%s%" PRIu32, "c", (uint32_t)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); @@ -901,7 +901,7 @@ static inline void printCImmediate(MCInst *MI, unsigned OpNum, SStream *O) static inline void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_CoprocOptionImm, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_CoprocOptionImm, OpNum); SStream_concat(O, "%s", "{"); printInt64(O, MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); SStream_concat0(O, "}"); @@ -911,7 +911,7 @@ static inline void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) static inline void CONCAT(printAdrLabelOperand, scale)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ + ARM_add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ OpNum, scale); \ MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \ \ @@ -945,7 +945,7 @@ DEFINE_printAdrLabelOperandAddr(2); static inline void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_ThumbS4ImmOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_ThumbS4ImmOperand, OpNum); SStream_concat(O, "%s", markup("")); @@ -953,7 +953,7 @@ static inline void printThumbS4ImmOperand(MCInst *MI, unsigned OpNum, static inline void printThumbSRImm(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_ThumbSRImm, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_ThumbSRImm, OpNum); unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); SStream_concat(O, "%s", markup("")); @@ -1382,7 +1382,7 @@ static inline void printFBits32(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorIndex, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorIndex, OpNum); SStream_concat(O, "%s", "["); printInt64(O, (int32_t)MCOperand_getImm(MCInst_getOperand(MI, (OpNum)))); @@ -1391,7 +1391,7 @@ static inline void printVectorIndex(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListOne, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListOne, OpNum); SStream_concat0(O, "{"); printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); SStream_concat0(O, "}"); @@ -1399,7 +1399,7 @@ static inline void printVectorListOne(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListTwo, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListTwo, OpNum); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); @@ -1413,7 +1413,7 @@ static inline void printVectorListTwo(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoSpaced, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListTwoSpaced, OpNum); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); @@ -1426,7 +1426,7 @@ static inline void printVectorListTwoSpaced(MCInst *MI, unsigned OpNum, static inline void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListThree, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListThree, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1441,7 +1441,7 @@ static inline void printVectorListThree(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListFour, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListFour, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1459,7 +1459,7 @@ static inline void printVectorListFour(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListOneAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListOneAllLanes, OpNum); SStream_concat0(O, "{"); printRegName(O, MCOperand_getReg(MCInst_getOperand(MI, (OpNum)))); SStream_concat0(O, "[]}"); @@ -1468,7 +1468,7 @@ static inline void printVectorListOneAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListTwoAllLanes, OpNum); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_1); @@ -1482,7 +1482,7 @@ static inline void printVectorListTwoAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListThreeAllLanes, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1498,7 +1498,7 @@ static inline void printVectorListThreeAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListFourAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListFourAllLanes, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1516,7 +1516,7 @@ static inline void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListTwoSpacedAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListTwoSpacedAllLanes, OpNum); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); @@ -1530,7 +1530,7 @@ static inline void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeSpacedAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListThreeSpacedAllLanes, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1546,7 +1546,7 @@ printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListFourSpacedAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListFourSpacedAllLanes, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1564,7 +1564,7 @@ static inline void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListThreeSpaced, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListThreeSpaced, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1580,7 +1580,7 @@ static inline void printVectorListThreeSpaced(MCInst *MI, unsigned OpNum, static inline void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VectorListFourSpaced, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListFourSpaced, OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1599,7 +1599,7 @@ static inline void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, static inline void CONCAT(printMVEVectorList, NumRegs)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ + ARM_add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ OpNum, NumRegs); \ unsigned Reg = \ MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ @@ -1620,7 +1620,7 @@ DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) CONCAT(Angle, Remainder))( \ MCInst * MI, unsigned OpNo, SStream *O) \ { \ - add_cs_detail_2( \ + ARM_add_cs_detail_2( \ MI, \ CONCAT(CONCAT(ARM_OP_GROUP_ComplexRotationOp, Angle), \ Remainder), \ @@ -1636,7 +1636,7 @@ DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VPTPredicateOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VPTPredicateOperand, OpNum); ARMVCC_VPTCodes CC = (ARMVCC_VPTCodes)MCOperand_getImm( MCInst_getOperand(MI, (OpNum))); if (CC != ARMVCC_None) @@ -1645,7 +1645,7 @@ DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) static inline void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_VPTMask, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VPTMask, OpNum); // (3 - the number of trailing zeroes) is the number of them / else. unsigned Mask = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); unsigned NumTZ = CountTrailingZeros_32(Mask); @@ -1662,7 +1662,7 @@ static inline void printVPTMask(MCInst *MI, unsigned OpNum, SStream *O) static inline void printMveSaturateOp(MCInst *MI, unsigned OpNum, SStream *O) { - add_cs_detail(MI, ARM_OP_GROUP_MveSaturateOp, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MveSaturateOp, OpNum); uint32_t Val = MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); printUInt32Bang(O, (Val == 1 ? 48 : 64)); diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 8be80e0852..9ee6a08f7f 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -1966,7 +1966,7 @@ static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group, /// Fills cs_detail with the data of the operand. /// Calls to this function are should not be added by hand! Please checkout the /// patch `AddCSDetail` of the CppTranslator. -void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, +static void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) { if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) @@ -2010,6 +2010,24 @@ void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, add_cs_detail_general(MI, op_group, op_num); } +void ARM_add_cs_detail_0(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num) +{ + ARM_add_cs_detail(MI, op_group, op_num, 0, 0); +} + +void ARM_add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num, uint64_t templ_arg_0) +{ + ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, 0); +} + +void ARM_add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) +{ + ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, templ_arg_1); +} + static void insert_op(MCInst *MI, unsigned index, cs_arm_op op) { if (!detail_is_set(MI)) { diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index bb547a4f8c..c7be90d183 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -51,31 +51,12 @@ void ARM_init_mri(MCRegisterInfo *MRI); // cs_detail related functions void ARM_init_cs_detail(MCInst *MI); -void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, +void ARM_add_cs_detail_0(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num); +void ARM_add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group, + size_t op_num, uint64_t templ_arg_0); +void ARM_add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group, size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1); -static inline void add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num) -{ - if (!detail_is_set(MI)) - return; - ARM_add_cs_detail(MI, op_group, op_num, 0, 0); -} - -static inline void add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0) -{ - if (!detail_is_set(MI)) - return; - ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, 0); -} - -static inline void add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) -{ - if (!detail_is_set(MI)) - return; - ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, templ_arg_1); -} void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, cs_ac_type access); diff --git a/arch/LoongArch/LoongArchInstPrinter.c b/arch/LoongArch/LoongArchInstPrinter.c index edb590dae5..4adf6c4b3c 100644 --- a/arch/LoongArch/LoongArchInstPrinter.c +++ b/arch/LoongArch/LoongArchInstPrinter.c @@ -91,7 +91,7 @@ static void printRegName(MCInst *MI, SStream *O, MCRegister Reg) static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) { - add_cs_detail(MI, LoongArch_OP_GROUP_Operand, OpNo); + LoongArch_add_cs_detail_0(MI, LoongArch_OP_GROUP_Operand, OpNo); MCOperand *MO = MCInst_getOperand(MI, (OpNo)); if (MCOperand_isReg(MO)) { @@ -134,7 +134,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) static void printAtomicMemOp(MCInst *MI, unsigned OpNo, SStream *O) { - add_cs_detail(MI, LoongArch_OP_GROUP_AtomicMemOp, OpNo); + LoongArch_add_cs_detail_0(MI, LoongArch_OP_GROUP_AtomicMemOp, OpNo); MCOperand *MO = MCInst_getOperand(MI, (OpNo)); printRegName(MI, O, MCOperand_getReg(MO)); diff --git a/arch/LoongArch/LoongArchMapping.c b/arch/LoongArch/LoongArchMapping.c index 17ba2b6e70..ec455169e7 100644 --- a/arch/LoongArch/LoongArchMapping.c +++ b/arch/LoongArch/LoongArchMapping.c @@ -536,7 +536,7 @@ void LoongArch_set_detail_op_reg(MCInst *MI, unsigned OpNum, loongarch_reg Reg) LoongArch_inc_op_count(MI); } -void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group, +void LoongArch_add_cs_detail_0(MCInst *MI, int /* loongarch_op_group */ op_group, size_t OpNum) { if (!detail_is_set(MI)) diff --git a/arch/LoongArch/LoongArchMapping.h b/arch/LoongArch/LoongArchMapping.h index 986ed84530..9bcc81ff99 100644 --- a/arch/LoongArch/LoongArchMapping.h +++ b/arch/LoongArch/LoongArchMapping.h @@ -38,14 +38,7 @@ bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len, // cs_detail related functions void LoongArch_init_cs_detail(MCInst *MI); -void LoongArch_add_cs_detail(MCInst *MI, int /* loongarch_op_group */ op_group, +void LoongArch_add_cs_detail_0(MCInst *MI, int /* loongarch_op_group */ op_group, size_t op_num); -static inline void add_cs_detail(MCInst *MI, - int /* loongarch_op_group */ op_group, size_t op_num) -{ - if (!detail_is_set(MI)) - return; - LoongArch_add_cs_detail(MI, op_group, op_num); -} #endif // CS_LOONGARCH_MAPPING_H diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c index deea347686..fa6e20ead7 100644 --- a/arch/Mips/MipsInstPrinter.c +++ b/arch/Mips/MipsInstPrinter.c @@ -274,7 +274,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O) MCOperand *Op = MCInst_getOperand(MI, (OpNo)); if (MCOperand_isReg(Op)) { - add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_Operand, OpNo); printRegName(MI, O, MCOperand_getReg(Op)); return; } @@ -300,7 +300,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O) (MI, OpNo, O); break; default: - add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_Operand, OpNo); printInt64(O, MCOperand_getImm(Op)); break; } @@ -310,7 +310,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O) static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O) { - add_cs_detail(MI, Mips_OP_GROUP_JumpOperand, OpNo); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_JumpOperand, OpNo); MCOperand *Op = MCInst_getOperand(MI, (OpNo)); if (MCOperand_isReg(Op)) return printRegName(MI, O, MCOperand_getReg(Op)); @@ -324,7 +324,7 @@ static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O) static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O) { - add_cs_detail(MI, Mips_OP_GROUP_BranchOperand, OpNo); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_BranchOperand, OpNo); MCOperand *Op = MCInst_getOperand(MI, (OpNo)); if (MCOperand_isReg(Op)) return printRegName(MI, O, MCOperand_getReg(Op)); @@ -337,7 +337,7 @@ static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \ SStream *O) \ { \ - add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \ + Mips_add_cs_detail_0(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \ opNum); \ MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ if (MCOperand_isImm(MO)) { \ @@ -354,7 +354,7 @@ static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, static void CONCAT(printUImm, CONCAT(Bits, Offset))( \ MCInst * MI, int opNum, SStream *O) \ { \ - add_cs_detail( \ + Mips_add_cs_detail_0( \ MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \ opNum); \ MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ @@ -436,7 +436,7 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O) case Mips_SHX_NM: case Mips_SHXS_NM: if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) { - add_cs_detail(MI, Mips_OP_GROUP_MemOperand, + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_MemOperand, (opNum + 1)); printRegName(MI, O, MCOperand_getImm(MCInst_getOperand( @@ -603,7 +603,7 @@ static void printRegisterList(MCInst *MI, int opNum, SStream *O) { // - 2 because register List is always first operand of instruction and it is // always followed by memory operand (base + offset). - add_cs_detail(MI, Mips_OP_GROUP_RegisterList, opNum); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_RegisterList, opNum); for (int i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) { if (i != opNum) SStream_concat0(O, ", "); @@ -614,7 +614,7 @@ static void printRegisterList(MCInst *MI, int opNum, SStream *O) static void printNanoMipsRegisterList(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum); for (unsigned I = OpNum; I < MCInst_getNumOperands(MI); I++) { SStream_concat0(O, ", "); printRegName(MI, O, @@ -626,7 +626,7 @@ static void printHi20(MCInst *MI, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MO)) { - add_cs_detail(MI, Mips_OP_GROUP_Hi20, OpNum); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_Hi20, OpNum); SStream_concat0(O, "%hi("); printUInt64(O, MCOperand_getImm(MO)); SStream_concat0(O, ")"); @@ -638,7 +638,7 @@ static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MO)) { - add_cs_detail(MI, Mips_OP_GROUP_Hi20PCRel, OpNum); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_Hi20PCRel, OpNum); SStream_concat0(O, "%pcrel_hi("); printUInt64(O, MCOperand_getImm(MO) + Address); SStream_concat0(O, ")"); @@ -650,7 +650,7 @@ static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O) { MCOperand *MO = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MO)) { - add_cs_detail(MI, Mips_OP_GROUP_PCRel, OpNum); + Mips_add_cs_detail_0(MI, Mips_OP_GROUP_PCRel, OpNum); printUInt64(O, MCOperand_getImm(MO) + Address); } else printOperand(MI, OpNum, O); diff --git a/arch/Mips/MipsMapping.c b/arch/Mips/MipsMapping.c index 9d096a6a8a..02385bd929 100644 --- a/arch/Mips/MipsMapping.c +++ b/arch/Mips/MipsMapping.c @@ -411,7 +411,7 @@ static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum) Mips_set_detail_op_imm(MI, OpNum, Target); } -void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, size_t OpNum) +void Mips_add_cs_detail_0(MCInst *MI, mips_op_group op_group, size_t OpNum) { if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) return; diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h index 97f403d3fa..a048666e9d 100644 --- a/arch/Mips/MipsMapping.h +++ b/arch/Mips/MipsMapping.h @@ -39,14 +39,7 @@ void Mips_init_cs_detail(MCInst *MI); void Mips_set_mem_access(MCInst *MI, bool status); -void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, size_t op_num); - -static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, size_t op_num) -{ - if (!detail_is_set(MI)) - return; - Mips_add_cs_detail(MI, op_group, op_num); -} +void Mips_add_cs_detail_0(MCInst *MI, mips_op_group op_group, size_t op_num); static inline void set_mem_access(MCInst *MI, bool status) { diff --git a/arch/SystemZ/SystemZInstPrinter.c b/arch/SystemZ/SystemZInstPrinter.c index 016d272a13..ee9eb18e79 100644 --- a/arch/SystemZ/SystemZInstPrinter.c +++ b/arch/SystemZ/SystemZInstPrinter.c @@ -216,80 +216,80 @@ DEFINE_printSImmOperand(32); static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U1ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U1ImmOperand, OpNum); CONCAT(printUImmOperand, 1)(MI, OpNum, O); } static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U2ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U2ImmOperand, OpNum); CONCAT(printUImmOperand, 2)(MI, OpNum, O); } static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U3ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U3ImmOperand, OpNum); CONCAT(printUImmOperand, 3)(MI, OpNum, O); } static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U4ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U4ImmOperand, OpNum); CONCAT(printUImmOperand, 4)(MI, OpNum, O); } static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_S8ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_S8ImmOperand, OpNum); CONCAT(printSImmOperand, 8)(MI, OpNum, O); } static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U8ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U8ImmOperand, OpNum); CONCAT(printUImmOperand, 8)(MI, OpNum, O); } static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U12ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U12ImmOperand, OpNum); CONCAT(printUImmOperand, 12)(MI, OpNum, O); } static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_S16ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_S16ImmOperand, OpNum); CONCAT(printSImmOperand, 16)(MI, OpNum, O); } static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U16ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U16ImmOperand, OpNum); CONCAT(printUImmOperand, 16)(MI, OpNum, O); } static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_S32ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_S32ImmOperand, OpNum); CONCAT(printSImmOperand, 32)(MI, OpNum, O); } static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U32ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U32ImmOperand, OpNum); CONCAT(printUImmOperand, 32)(MI, OpNum, O); } static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_U48ImmOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_U48ImmOperand, OpNum); CONCAT(printUImmOperand, 48)(MI, OpNum, O); } static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_PCRelOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_PCRelOperand, OpNum); MCOperand *MO = MCInst_getOperand(MI, (OpNum)); if (MCOperand_isImm(MO)) { printInt64(O, MCOperand_getImm(MO)); @@ -311,20 +311,20 @@ static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum, static void printOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_Operand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_Operand, OpNum); printMCOperand(MI, MCInst_getOperand(MI, (OpNum)), O); } static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_BDAddrOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDAddrOperand, OpNum); printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))), MCInst_getOperand(MI, (OpNum + 1)), 0, O); } static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_BDXAddrOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDXAddrOperand, OpNum); printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))), MCInst_getOperand(MI, (OpNum + 1)), MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O); @@ -332,7 +332,7 @@ static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O) static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_BDLAddrOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDLAddrOperand, OpNum); unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1)); uint64_t Length = MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 2))); @@ -348,7 +348,7 @@ static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O) static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_BDRAddrOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDRAddrOperand, OpNum); unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1)); unsigned Length = MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))); @@ -364,7 +364,7 @@ static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O) static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_BDVAddrOperand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_BDVAddrOperand, OpNum); printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))), MCInst_getOperand(MI, (OpNum + 1)), MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O); @@ -372,7 +372,7 @@ static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O) static void printCond4Operand(MCInst *MI, int OpNum, SStream *O) { - add_cs_detail(MI, SystemZ_OP_GROUP_Cond4Operand, OpNum); + SystemZ_add_cs_detail_0(MI, SystemZ_OP_GROUP_Cond4Operand, OpNum); static const char *const CondNames[] = { "o", "h", "nle", "l", "nhe", "lh", "ne", "e", "nlh", "he", "nl", "le", diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c index 78bdf48936..8cbfb4f1a7 100644 --- a/arch/SystemZ/SystemZMapping.c +++ b/arch/SystemZ/SystemZMapping.c @@ -159,7 +159,7 @@ const char *SystemZ_group_name(csh handle, unsigned int id) #endif } -void SystemZ_add_cs_detail(MCInst *MI, int /* systemz_op_group */ op_group, +void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group, size_t op_num) { #ifndef CAPSTONE_DIET diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 230a599e71..00821371d7 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -36,15 +36,7 @@ void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm, void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am); -void SystemZ_add_cs_detail(MCInst *MI, int /* systemz_op_group */ op_group, +void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group, size_t op_num); -static inline void add_cs_detail(MCInst *MI, - int /* systemz_op_group */ op_group, size_t op_num) -{ - if (!detail_is_set(MI)) - return; - SystemZ_add_cs_detail(MI, op_group, op_num); -} - #endif // CS_SYSTEMZ_MAP_H diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index 3b266563d7..612f400a22 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -116,7 +116,7 @@ def get_add_cs_detail( ) elif op_group_enum == b"ARM_OP_GROUP_RegImmShift": return ( - f"{self.arch}_add_cs_detail_1(MI, ".encode() + f"{self.arch}_add_cs_detail_2(MI, ".encode() + op_group_enum + b", ShOpc, ShImm);" ) From 2b3deaee52be01e55fc97901ec279b56108fa17b Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 13 Feb 2026 15:20:14 +0100 Subject: [PATCH 15/16] Add job to build cross compiled packages. --- .github/workflows/CrossBuilds.yml | 80 +++++++++++++++++++++++++++---- 1 file changed, 71 insertions(+), 9 deletions(-) diff --git a/.github/workflows/CrossBuilds.yml b/.github/workflows/CrossBuilds.yml index 77d5942791..e8a2885ff5 100644 --- a/.github/workflows/CrossBuilds.yml +++ b/.github/workflows/CrossBuilds.yml @@ -16,6 +16,8 @@ on: - "SPONSORS.TXT" - "TODO" pull_request: + release: + types: [published] # Stop previous runs on the same branch on new push concurrency: @@ -42,7 +44,9 @@ jobs: arch: x64, build-system: 'cmake', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_s390x', + build_exe: false, diet_build: false, packages: 'gcc-s390x-linux-gnu g++-s390x-linux-gnu binutils-s390x-linux-gnu libc6-dev-s390x-cross qemu-user-static', cross_file: 'cross_configs/linux_s390x_ubuntu24.cmake', @@ -53,7 +57,9 @@ jobs: arch: x64, build-system: 'cmake', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_mips32', + build_exe: false, diet_build: false, packages: 'gcc-mips-linux-gnu g++-mips-linux-gnu binutils-mips-linux-gnu libc6-dev-mips-cross qemu-user-static', cross_file: 'cross_configs/linux_mips_ubuntu24.cmake', @@ -64,7 +70,9 @@ jobs: arch: x64, build-system: 'cmake', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_mips64el', + build_exe: false, diet_build: false, packages: 'gcc-mips64el-linux-gnuabi64 g++-mips64el-linux-gnuabi64 binutils-mips64el-linux-gnuabi64 libc6-dev-mips64el-cross qemu-user-static', cross_file: 'cross_configs/linux_mips64_ubuntu24.cmake', @@ -75,7 +83,9 @@ jobs: arch: x64, build-system: 'cmake', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_ppc64', + build_exe: false, diet_build: false, packages: 'gcc-powerpc64-linux-gnu g++-powerpc64-linux-gnu binutils-powerpc64-linux-gnu libc6-dev-ppc64-cross qemu-user-static', cross_file: 'cross_configs/linux_ppc64_ubuntu24.cmake', @@ -86,7 +96,9 @@ jobs: arch: x64, build-system: 'cmake', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_arm_v7', + build_exe: false, diet_build: false, packages: 'gcc-arm-linux-gnueabihf g++-arm-linux-gnueabihf binutils-arm-linux-gnueabihf libc6-armhf-cross libc6-dev-armhf-cross qemu-user-static', cross_file: 'cross_configs/linux_arm_ubuntu24.cmake', @@ -97,10 +109,13 @@ jobs: arch: x64, build-system: 'cmake', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_win_i686', + build_exe: true, diet_build: false, + # Tests are run via Python. skip_tests: true, - packages: 'gcc-mingw-w64-i686 g++-mingw-w64-i686 mingw-w64-tools', + packages: 'gcc-mingw-w64-i686 g++-mingw-w64-i686 mingw-w64-tools nsis', cross_file: 'cross_configs/windows_i686_ubuntu24.cmake', } - { @@ -110,10 +125,12 @@ jobs: build-system: 'cmake', build_option: '-DANDROID_NDK=ndk/ -DANDROID_PLATFORM=android-35 -DANDROID_ABI=arm64-v8a', diet-build: 'OFF', - build_type: 'Debug', + build_type: 'Release', + upload_name: 'capstone_android_35_arm64_v8a', + build_exe: false, diet_build: false, # QEMU alone can't emulate the binaries, because the NDK doesn't - # provide dynamic linker. + # provide a dynamic linker. skip_tests: true, packages: 'qemu-user-static', ndk_version: 'r29', @@ -200,3 +217,48 @@ jobs: if: ${{ matrix.config.skip_tests != true }} run: | ctest --test-dir build --output-on-failure -R legacy* + + - name: Package binary tar.gz + if: ${{ matrix.config.build_exe == false }} + run: | + cd build + cpack -G TGZ + + - uses: actions/upload-artifact@v4 + if: ${{ matrix.config.build_exe == false }} + with: + name: ${{ matrix.config.upload_name }} + path: ./build/*.tar.gz + + - name: Upload binary package to release + uses: softprops/action-gh-release@v2 + if: startsWith(github.ref, 'refs/tags') && github.event_name == 'release' && matrix.config.build_exe == false + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: ${{ github.event.release.tag_name }} + files: | + ./build/*.tar.gz + + - name: Package NSIS installer + if: ${{ matrix.config.build_exe }} + run: | + makensis -VERSION + cd build + cpack -G NSIS + + - uses: actions/upload-artifact@v4 + if: ${{ matrix.config.build_exe }} + with: + name: ${{ matrix.config.upload_name }} + path: ./build/capstone-*.exe + + - name: Upload NSIS installer to release + uses: softprops/action-gh-release@v2 + if: startsWith(github.ref, 'refs/tags') && github.event_name == 'release' && matrix.config.build_exe + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: ${{ github.event.release.tag_name }} + files: | + ./build/capstone-*.exe From 163e77b40067ca27f1975b647b9ea21fef29997d Mon Sep 17 00:00:00 2001 From: Rot127 Date: Fri, 13 Feb 2026 16:41:41 +0100 Subject: [PATCH 16/16] Run clang-format-17 --- arch/AArch64/AArch64InstPrinter.c | 3 +- arch/AArch64/AArch64Mapping.c | 12 +++-- arch/AArch64/AArch64Mapping.h | 3 +- arch/ARC/ARCMapping.h | 2 +- arch/ARM/ARMInstPrinter.c | 82 +++++++++++++++++-------------- arch/ARM/ARMMapping.c | 10 ++-- arch/ARM/ARMMapping.h | 7 +-- arch/LoongArch/LoongArchMapping.c | 5 +- arch/LoongArch/LoongArchMapping.h | 5 +- arch/M68K/M68KInstPrinter.c | 24 +++++---- arch/Mips/MipsInstPrinter.c | 7 +-- arch/SystemZ/SystemZMapping.c | 2 +- arch/SystemZ/SystemZMapping.h | 2 +- suite/cstest/src/helper.c | 9 ++-- 14 files changed, 102 insertions(+), 71 deletions(-) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 29d00d6952..59278cac81 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -2319,7 +2319,8 @@ void printSIMDType10Operand(MCInst *MI, unsigned OpNo, SStream *O) unsigned Val = \ MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ SStream_concat(O, "%s", markup("")); \ } DEFINE_printComplexRotationOp(180, 90); diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index c8e10f4b31..23da9f026a 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -1668,7 +1668,8 @@ void AArch64_add_cs_detail_0(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE_LIST, AARCH64LAYOUT_VL_D, - (int)(AARCH64_REG_ZAD0 + I), 0); + (int)(AARCH64_REG_ZAD0 + I), + 0); AArch64_inc_op_count(MI); } AArch64_get_detail(MI)->is_doing_sme = false; @@ -1976,7 +1977,8 @@ void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_Matrix_64: { unsigned EltSize = temp_arg_0; AArch64_set_detail_op_sme(MI, OpNum, AARCH64_SME_MATRIX_TILE, - (AArch64Layout_VectorLayout)EltSize, 0, 0); + (AArch64Layout_VectorLayout)EltSize, + 0, 0); break; } case AArch64_OP_GROUP_MatrixIndex_0: @@ -1988,7 +1990,8 @@ void AArch64_add_cs_detail_1(MCInst *MI, aarch64_op_group op_group, AArch64_set_detail_op_sme( MI, OpNum, AARCH64_SME_MATRIX_SLICE_OFF, AARCH64LAYOUT_INVALID, - (uint32_t)(MCInst_getOpVal(MI, OpNum) * scale), 0); + (uint32_t)(MCInst_getOpVal(MI, OpNum) * scale), + 0); } else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) { // The index is part of a predicate @@ -2720,7 +2723,8 @@ void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum) /// Adds a SME matrix component to a SME operand. void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, aarch64_sme_op_part part, - AArch64Layout_VectorLayout vas, uint64_t arg_0, uint64_t arg_1) + AArch64Layout_VectorLayout vas, uint64_t arg_0, + uint64_t arg_1) { if (!detail_is_set(MI)) return; diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index 85ff6930ac..45d3b2dbe2 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -75,7 +75,8 @@ void AArch64_set_detail_op_sys(MCInst *MI, unsigned OpNum, aarch64_sysop sys_op, aarch64_op_type type); void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum, aarch64_sme_op_part part, - AArch64Layout_VectorLayout vas, uint64_t arg_0, uint64_t arg_1); + AArch64Layout_VectorLayout vas, uint64_t arg_0, + uint64_t arg_1); void AArch64_set_detail_op_pred(MCInst *MI, unsigned OpNum); void AArch64_insert_detail_op_reg_at(MCInst *MI, unsigned index, aarch64_reg Reg, cs_ac_type access); diff --git a/arch/ARC/ARCMapping.h b/arch/ARC/ARCMapping.h index 25fff8cebe..cf207ae71b 100644 --- a/arch/ARC/ARCMapping.h +++ b/arch/ARC/ARCMapping.h @@ -39,6 +39,6 @@ void ARC_init_cs_detail(MCInst *MI); void ARC_set_detail_op_imm(MCInst *MI, unsigned OpNum, arc_op_type ImmType, int64_t Imm); void ARC_add_cs_detail_0(MCInst *MI, int /* arc_op_group */ op_group, - size_t op_num); + size_t op_num); #endif diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index ffe0f40c03..2c23861784 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -407,9 +407,9 @@ static inline void printAM3PreOrOffsetIndexOp(MCInst *MI, unsigned Op, MCInst * MI, unsigned Op, SStream *O) \ { \ ARM_add_cs_detail_1(MI, \ - CONCAT(ARM_OP_GROUP_AddrMode3Operand, \ - AlwaysPrintImm0), \ - Op, AlwaysPrintImm0); \ + CONCAT(ARM_OP_GROUP_AddrMode3Operand, \ + AlwaysPrintImm0), \ + Op, AlwaysPrintImm0); \ MCOperand *MO1 = MCInst_getOperand(MI, (Op)); \ if (!MCOperand_isReg(MO1)) { \ printOperand(MI, Op, O); \ @@ -515,9 +515,9 @@ DEFINE_printMveAddrModeRQOperand(2); MCInst * MI, unsigned OpNum, SStream *O) \ { \ ARM_add_cs_detail_1(MI, \ - CONCAT(ARM_OP_GROUP_AddrMode5Operand, \ - AlwaysPrintImm0), \ - OpNum, AlwaysPrintImm0); \ + CONCAT(ARM_OP_GROUP_AddrMode5Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ \ @@ -544,9 +544,9 @@ DEFINE_printAddrMode5Operand(true); MCInst * MI, unsigned OpNum, SStream *O) \ { \ ARM_add_cs_detail_1(MI, \ - CONCAT(ARM_OP_GROUP_AddrMode5FP16Operand, \ - AlwaysPrintImm0), \ - OpNum, AlwaysPrintImm0); \ + CONCAT(ARM_OP_GROUP_AddrMode5FP16Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ \ @@ -858,8 +858,8 @@ static inline void printMandatoryPredicateOperand(MCInst *MI, unsigned OpNum, static inline void printMandatoryRestrictedPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MandatoryRestrictedPredicateOperand, - OpNum); + ARM_add_cs_detail_0( + MI, ARM_OP_GROUP_MandatoryRestrictedPredicateOperand, OpNum); if ((ARMCC_CondCodes)MCOperand_getImm(MCInst_getOperand(MI, (OpNum))) == ARMCC_HS) SStream_concat0(O, "cs"); @@ -871,7 +871,7 @@ static inline void printMandatoryInvertedPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O) { ARM_add_cs_detail_0(MI, ARM_OP_GROUP_MandatoryInvertedPredicateOperand, - OpNum); + OpNum); ARMCC_CondCodes CC = (ARMCC_CondCodes)MCOperand_getImm( MCInst_getOperand(MI, (OpNum))); SStream_concat0(O, ARMCondCodeToString(ARMCC_getOppositeCondition(CC))); @@ -911,8 +911,9 @@ static inline void printCoprocOptionImm(MCInst *MI, unsigned OpNum, SStream *O) static inline void CONCAT(printAdrLabelOperand, scale)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - ARM_add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ - OpNum, scale); \ + ARM_add_cs_detail_1( \ + MI, CONCAT(ARM_OP_GROUP_AdrLabelOperand, scale), \ + OpNum, scale); \ MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \ \ if (MCOperand_isExpr(MO)) { \ @@ -1079,9 +1080,9 @@ static inline void printT2SOOperand(MCInst *MI, unsigned OpNum, SStream *O) MCInst * MI, unsigned OpNum, SStream *O) \ { \ ARM_add_cs_detail_1(MI, \ - CONCAT(ARM_OP_GROUP_AddrModeImm12Operand, \ - AlwaysPrintImm0), \ - OpNum, AlwaysPrintImm0); \ + CONCAT(ARM_OP_GROUP_AddrModeImm12Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ \ @@ -1120,9 +1121,9 @@ DEFINE_printAddrModeImm12Operand(true); unsigned OpNum, SStream *O) \ { \ ARM_add_cs_detail_1(MI, \ - CONCAT(ARM_OP_GROUP_T2AddrModeImm8Operand, \ - AlwaysPrintImm0), \ - OpNum, AlwaysPrintImm0); \ + CONCAT(ARM_OP_GROUP_T2AddrModeImm8Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ \ @@ -1155,10 +1156,11 @@ DEFINE_printT2AddrModeImm8Operand(false); AlwaysPrintImm0)(MCInst * MI, \ unsigned OpNum, SStream *O) \ { \ - ARM_add_cs_detail_1(MI, \ - CONCAT(ARM_OP_GROUP_T2AddrModeImm8s4Operand, \ - AlwaysPrintImm0), \ - OpNum, AlwaysPrintImm0); \ + ARM_add_cs_detail_1( \ + MI, \ + CONCAT(ARM_OP_GROUP_T2AddrModeImm8s4Operand, \ + AlwaysPrintImm0), \ + OpNum, AlwaysPrintImm0); \ MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); \ MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); \ \ @@ -1195,7 +1197,8 @@ DEFINE_printT2AddrModeImm8s4Operand(true); static inline void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand, + OpNum); MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); MCOperand *MO2 = MCInst_getOperand(MI, (OpNum + 1)); @@ -1214,7 +1217,8 @@ static inline void printT2AddrModeImm0_1020s4Operand(MCInst *MI, unsigned OpNum, static inline void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_T2AddrModeImm8OffsetOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_T2AddrModeImm8OffsetOperand, + OpNum); MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); int32_t OffImm = (int32_t)MCOperand_getImm(MO1); SStream_concat(O, "%s", ", "); @@ -1232,7 +1236,8 @@ static inline void printT2AddrModeImm8OffsetOperand(MCInst *MI, unsigned OpNum, static inline void printT2AddrModeImm8s4OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand, + OpNum); MCOperand *MO1 = MCInst_getOperand(MI, (OpNum)); int32_t OffImm = (int32_t)MCOperand_getImm(MO1); @@ -1366,9 +1371,9 @@ static inline void printFBits16(MCInst *MI, unsigned OpNum, SStream *O) { ARM_add_cs_detail_0(MI, ARM_OP_GROUP_FBits16, OpNum); SStream_concat(O, "%s%s", markup("")); } @@ -1516,7 +1521,8 @@ static inline void printVectorListFourAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListTwoSpacedAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListTwoSpacedAllLanes, + OpNum); unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); unsigned Reg0 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_0); unsigned Reg1 = MCRegisterInfo_getSubReg(MI->MRI, Reg, ARM_dsub_2); @@ -1530,7 +1536,8 @@ static inline void printVectorListTwoSpacedAllLanes(MCInst *MI, unsigned OpNum, static inline void printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListThreeSpacedAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListThreeSpacedAllLanes, + OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1546,7 +1553,8 @@ printVectorListThreeSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) static inline void printVectorListFourSpacedAllLanes(MCInst *MI, unsigned OpNum, SStream *O) { - ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListFourSpacedAllLanes, OpNum); + ARM_add_cs_detail_0(MI, ARM_OP_GROUP_VectorListFourSpacedAllLanes, + OpNum); // Normally, it's not safe to use register enum values directly with // addition to get the next register, but for VFP registers, the // sort order is guaranteed because they're all of the form D. @@ -1599,8 +1607,9 @@ static inline void printVectorListFourSpaced(MCInst *MI, unsigned OpNum, static inline void CONCAT(printMVEVectorList, NumRegs)( \ MCInst * MI, unsigned OpNum, SStream *O) \ { \ - ARM_add_cs_detail_1(MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ - OpNum, NumRegs); \ + ARM_add_cs_detail_1( \ + MI, CONCAT(ARM_OP_GROUP_MVEVectorList, NumRegs), \ + OpNum, NumRegs); \ unsigned Reg = \ MCOperand_getReg(MCInst_getOperand(MI, (OpNum))); \ const char *Prefix = "{"; \ @@ -1627,7 +1636,8 @@ DEFINE_printMVEVectorList(2) DEFINE_printMVEVectorList(4) OpNo, Angle, Remainder); \ unsigned Val = \ MCOperand_getImm(MCInst_getOperand(MI, (OpNo))); \ - SStream_concat(O, "#%u", (uint32_t)((Val * Angle) + Remainder)); \ + SStream_concat(O, "#%u", \ + (uint32_t)((Val * Angle) + Remainder)); \ } DEFINE_printComplexRotationOp(90, 0) DEFINE_printComplexRotationOp(180, 90) diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 9ee6a08f7f..c01a206563 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -1967,7 +1967,8 @@ static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group, /// Calls to this function are should not be added by hand! Please checkout the /// patch `AddCSDetail` of the CppTranslator. static void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) + size_t op_num, uint64_t templ_arg_0, + uint64_t templ_arg_1) { if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) return; @@ -2011,19 +2012,20 @@ static void ARM_add_cs_detail(MCInst *MI, int /* arm_op_group */ op_group, } void ARM_add_cs_detail_0(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num) + size_t op_num) { ARM_add_cs_detail(MI, op_group, op_num, 0, 0); } void ARM_add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0) + size_t op_num, uint64_t templ_arg_0) { ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, 0); } void ARM_add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1) + size_t op_num, uint64_t templ_arg_0, + uint64_t templ_arg_1) { ARM_add_cs_detail(MI, op_group, op_num, templ_arg_0, templ_arg_1); } diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index c7be90d183..6266d12b01 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -52,11 +52,12 @@ void ARM_init_mri(MCRegisterInfo *MRI); // cs_detail related functions void ARM_init_cs_detail(MCInst *MI); void ARM_add_cs_detail_0(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num); + size_t op_num); void ARM_add_cs_detail_1(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0); + size_t op_num, uint64_t templ_arg_0); void ARM_add_cs_detail_2(MCInst *MI, int /* arm_op_group */ op_group, - size_t op_num, uint64_t templ_arg_0, uint64_t templ_arg_1); + size_t op_num, uint64_t templ_arg_0, + uint64_t templ_arg_1); void ARM_insert_detail_op_reg_at(MCInst *MI, unsigned index, arm_reg Reg, cs_ac_type access); diff --git a/arch/LoongArch/LoongArchMapping.c b/arch/LoongArch/LoongArchMapping.c index ec455169e7..83b07271cd 100644 --- a/arch/LoongArch/LoongArchMapping.c +++ b/arch/LoongArch/LoongArchMapping.c @@ -536,8 +536,9 @@ void LoongArch_set_detail_op_reg(MCInst *MI, unsigned OpNum, loongarch_reg Reg) LoongArch_inc_op_count(MI); } -void LoongArch_add_cs_detail_0(MCInst *MI, int /* loongarch_op_group */ op_group, - size_t OpNum) +void LoongArch_add_cs_detail_0(MCInst *MI, + int /* loongarch_op_group */ op_group, + size_t OpNum) { if (!detail_is_set(MI)) return; diff --git a/arch/LoongArch/LoongArchMapping.h b/arch/LoongArch/LoongArchMapping.h index 9bcc81ff99..9c6169ff3d 100644 --- a/arch/LoongArch/LoongArchMapping.h +++ b/arch/LoongArch/LoongArchMapping.h @@ -38,7 +38,8 @@ bool LoongArch_getInstruction(csh handle, const uint8_t *code, size_t code_len, // cs_detail related functions void LoongArch_init_cs_detail(MCInst *MI); -void LoongArch_add_cs_detail_0(MCInst *MI, int /* loongarch_op_group */ op_group, - size_t op_num); +void LoongArch_add_cs_detail_0(MCInst *MI, + int /* loongarch_op_group */ op_group, + size_t op_num); #endif // CS_LOONGARCH_MAPPING_H diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c index 38c3fdff2e..af730a7a5a 100644 --- a/arch/M68K/M68KInstPrinter.c +++ b/arch/M68K/M68KInstPrinter.c @@ -128,7 +128,8 @@ static void printRegbitsRange(char *buffer, size_t buf_len, uint32_t data, prefix, first); if (run_length > 0) snprintf(buffer + strlen(buffer), buf_len, - "-%s%" PRId32, prefix, first + run_length); + "-%s%" PRId32, prefix, + first + run_length); } } } @@ -194,8 +195,8 @@ static void printAddressingMode(SStream *O, unsigned int pc, SStream_concat(O, "-(a%" PRId32 ")", (op->reg - M68K_REG_A0)); break; case M68K_AM_REGI_ADDR_DISP: - SStream_concat(O, "%s$%" PRIx16 "(a%" PRId32 ")", op->mem.disp < 0 ? "-" : "", - abs(op->mem.disp), + SStream_concat(O, "%s$%" PRIx16 "(a%" PRId32 ")", + op->mem.disp < 0 ? "-" : "", abs(op->mem.disp), (op->mem.base_reg - M68K_REG_A0)); break; case M68K_AM_PCI_DISP: @@ -226,8 +227,9 @@ static void printAddressingMode(SStream *O, unsigned int pc, SStream_concat(O, "#$%" PRIx64, op->imm); break; case M68K_AM_PCI_INDEX_8_BIT_DISP: - SStream_concat(O, "$%" PRIx32 "(pc,%s%s.%c)", pc + 2 + op->mem.disp, - s_spacing, getRegName(op->mem.index_reg), + SStream_concat(O, "$%" PRIx32 "(pc,%s%s.%c)", + pc + 2 + op->mem.disp, s_spacing, + getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w'); break; case M68K_AM_AREGI_INDEX_8_BIT_DISP: @@ -241,7 +243,8 @@ static void printAddressingMode(SStream *O, unsigned int pc, case M68K_AM_AREGI_INDEX_BASE_DISP: if (op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP) { - SStream_concat(O, "$%" PRIx32, pc + 2 + op->mem.in_disp); + SStream_concat(O, "$%" PRIx32, + pc + 2 + op->mem.in_disp); } else if (op->mem.in_disp != 0) { SStream_concat(O, "%s$%" PRIx32, op->mem.in_disp >= 0 ? "" : "-", @@ -284,7 +287,8 @@ static void printAddressingMode(SStream *O, unsigned int pc, if (op->address_mode == M68K_AM_PC_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_PRE_INDEX) { - SStream_concat(O, "$%" PRIx32, pc + 2 + op->mem.in_disp); + SStream_concat(O, "$%" PRIx32, + pc + 2 + op->mem.in_disp); } else if (op->mem.in_disp != 0) { SStream_concat(O, "%s$%" PRIx32, op->mem.in_disp >= 0 ? "" : "-", @@ -332,7 +336,8 @@ static void printAddressingMode(SStream *O, unsigned int pc, } if (op->mem.bitfield) - SStream_concat(O, "{%" PRId8 ":%" PRId8 "}", op->mem.offset, op->mem.width); + SStream_concat(O, "{%" PRId8 ":%" PRId8 "}", op->mem.offset, + op->mem.width); } #endif @@ -374,7 +379,8 @@ void M68K_printInst(MCInst *MI, SStream *O, void *PrinterInfo) if (MI->Opcode == M68K_INS_INVALID) { if (ext->op_count) - SStream_concat(O, "dc.w $%" PRIx32, ext->operands[0].imm); + SStream_concat(O, "dc.w $%" PRIx32, + ext->operands[0].imm); else SStream_concat(O, "dc.w $"); return; diff --git a/arch/Mips/MipsInstPrinter.c b/arch/Mips/MipsInstPrinter.c index fa6e20ead7..8353f64488 100644 --- a/arch/Mips/MipsInstPrinter.c +++ b/arch/Mips/MipsInstPrinter.c @@ -337,8 +337,9 @@ static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \ SStream *O) \ { \ - Mips_add_cs_detail_0(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \ - opNum); \ + Mips_add_cs_detail_0( \ + MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), \ + opNum); \ MCOperand *MO = MCInst_getOperand(MI, (opNum)); \ if (MCOperand_isImm(MO)) { \ uint64_t Imm = MCOperand_getImm(MO); \ @@ -437,7 +438,7 @@ static void printMemOperand(MCInst *MI, int opNum, SStream *O) case Mips_SHXS_NM: if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) { Mips_add_cs_detail_0(MI, Mips_OP_GROUP_MemOperand, - (opNum + 1)); + (opNum + 1)); printRegName(MI, O, MCOperand_getImm(MCInst_getOperand( MI, (opNum + 1)))); diff --git a/arch/SystemZ/SystemZMapping.c b/arch/SystemZ/SystemZMapping.c index 8cbfb4f1a7..0e42613cca 100644 --- a/arch/SystemZ/SystemZMapping.c +++ b/arch/SystemZ/SystemZMapping.c @@ -160,7 +160,7 @@ const char *SystemZ_group_name(csh handle, unsigned int id) } void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group, - size_t op_num) + size_t op_num) { #ifndef CAPSTONE_DIET if (!detail_is_set(MI) || !map_fill_detail_ops(MI)) diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 00821371d7..ad068c6575 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -37,6 +37,6 @@ void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am); void SystemZ_add_cs_detail_0(MCInst *MI, int /* systemz_op_group */ op_group, - size_t op_num); + size_t op_num); #endif // CS_SYSTEMZ_MAP_H diff --git a/suite/cstest/src/helper.c b/suite/cstest/src/helper.c index b22a2a94ee..b34f62aad5 100644 --- a/suite/cstest/src/helper.c +++ b/suite/cstest/src/helper.c @@ -12,7 +12,8 @@ #include "cmocka.h" #include "helper.h" -char *cs_strndup(const char *s, size_t n) { +char *cs_strndup(const char *s, size_t n) +{ if (!s) { return NULL; } @@ -138,10 +139,12 @@ void replace_negative(char *src, size_t src_len, size_t arch_bits) add_str(&result, "%s%hu", tmp_tmp, tmp_short); } else if (arch_bits == 32) { sscanf(value, "%" PRIu32, &tmp_int); - add_str(&result, "%s%" PRIu32, tmp_tmp, tmp_int); + add_str(&result, "%s%" PRIu32, tmp_tmp, + tmp_int); } else if (arch_bits == 64) { sscanf(value, "%" PRIu64, &tmp_long); - add_str(&result, "%s%" PRIu64, tmp_tmp, tmp_long); + add_str(&result, "%s%" PRIu64, tmp_tmp, + tmp_long); } } else