EUnew.bdf

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2020  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/
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	(pt 1440 584)
	(pt 1544 584)
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)
(connector
	(pt 1432 600)
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)
(connector
	(pt 1480 616)
	(pt 1544 616)
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)
(connector
	(pt 1520 632)
	(pt 1544 632)
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)
(junction (pt 1408 400))
(junction (pt 1168 176))
(junction (pt 1168 312))
(junction (pt 1152 432))
(junction (pt 1152 176))
(junction (pt 1144 576))
(junction (pt 1440 584))
(junction (pt 1432 600))
(junction (pt 1200 416))
(junction (pt 1200 560))
(junction (pt 1144 176))
(junction (pt 1928 992))
(junction (pt 1904 992))
(junction (pt 1392 544))
(junction (pt 1448 568))
(junction (pt 1432 280))