From c68d93c881937c5182118f93896930087790b448 Mon Sep 17 00:00:00 2001 From: Marylise Monchalin Date: Mon, 30 Mar 2026 17:40:09 -0400 Subject: [PATCH 1/2] CortexM: expose RequestTranslationBlockInterrupt for precise bus fault modeling --- src/Emulator/Cores/Arm-M/CortexM.cs | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/Emulator/Cores/Arm-M/CortexM.cs b/src/Emulator/Cores/Arm-M/CortexM.cs index 3f26cb466..638dca0a6 100644 --- a/src/Emulator/Cores/Arm-M/CortexM.cs +++ b/src/Emulator/Cores/Arm-M/CortexM.cs @@ -670,6 +670,17 @@ public UInt32 FaultStatus } } + /// + /// Requests an abort of the currently executing instruction inside the + /// translation block. When excludeLastInstruction is true the CPU state + /// is restored to the start of the faulting instruction (PC points to + /// it), modelling a synchronous precise fault that can be retried. + /// + public void RequestTranslationBlockInterrupt(bool excludeLastInstruction) + { + TlibRequestTranslationBlockInterrupt(excludeLastInstruction ? 1 : 0); + } + public bool SecureState { get From e756275c40cba8df8d12578866aae94060e6c38f Mon Sep 17 00:00:00 2001 From: Marylise Monchalin Date: Tue, 5 May 2026 11:29:20 -0400 Subject: [PATCH 2/2] Move RequestTranslationBlockInterrupt to TranslationCPU per review --- src/Emulator/Cores/Arm-M/CortexM.cs | 11 ----------- .../Peripherals/Peripherals/CPU/TranslationCPU.cs | 12 ++++++++++++ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/Emulator/Cores/Arm-M/CortexM.cs b/src/Emulator/Cores/Arm-M/CortexM.cs index 638dca0a6..3f26cb466 100644 --- a/src/Emulator/Cores/Arm-M/CortexM.cs +++ b/src/Emulator/Cores/Arm-M/CortexM.cs @@ -670,17 +670,6 @@ public UInt32 FaultStatus } } - /// - /// Requests an abort of the currently executing instruction inside the - /// translation block. When excludeLastInstruction is true the CPU state - /// is restored to the start of the faulting instruction (PC points to - /// it), modelling a synchronous precise fault that can be retried. - /// - public void RequestTranslationBlockInterrupt(bool excludeLastInstruction) - { - TlibRequestTranslationBlockInterrupt(excludeLastInstruction ? 1 : 0); - } - public bool SecureState { get diff --git a/src/Emulator/Peripherals/Peripherals/CPU/TranslationCPU.cs b/src/Emulator/Peripherals/Peripherals/CPU/TranslationCPU.cs index 3411f5f0d..7257e4a6c 100644 --- a/src/Emulator/Peripherals/Peripherals/CPU/TranslationCPU.cs +++ b/src/Emulator/Peripherals/Peripherals/CPU/TranslationCPU.cs @@ -432,6 +432,18 @@ public bool RequestTranslationBlockRestart(bool quiet = false) return pauseGuard.RequestTranslationBlockRestart(quiet); } + /// + /// Requests an abort of the currently executing instruction inside the + /// translation block. When is + /// true the CPU state is restored to the start of the faulting + /// instruction (PC points to it), modelling a synchronous precise fault + /// that can be retried. + /// + public void RequestTranslationBlockInterrupt(bool excludeLastInstruction) + { + TlibRequestTranslationBlockInterrupt(excludeLastInstruction ? 1 : 0); + } + public uint AssembleBlock(ulong addr, string instructions, string triple = null, bool alternateDialect = false) { if(Assembler == null)