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ld pin missing in RAM "Separate load and store ports" mode (Regression since 2.16.1.4)

Status: Open.

#46 In Logisim-Ita/Logisim;

· KEDIT2007 opened on May 16, 2026

A Defect in the Simulation of Transistors

Status: Open.

#39 In Logisim-Ita/Logisim;

· Pure-Happiness opened on Mar 30, 2025

error in xor and xnor gate output with 3 inputs

Status: Open.

#36 In Logisim-Ita/Logisim;

· yamel-panda opened on Oct 5, 2023

PLA ROM in subcircuit makes clock stop working

Status: Open.

#22 In Logisim-Ita/Logisim;

· maehne opened on Nov 2, 2021

Need support for Hi-dpi

Status: Open.

#19 In Logisim-Ita/Logisim;

· ZJsheep opened on Apr 27, 2021

Input/Output Pin

Status: Open.

#16 In Logisim-Ita/Logisim;

· JimmyDansbo opened on Aug 28, 2020

wire's colors change when you move it

Status: Open.

#12 In Logisim-Ita/Logisim;

· piegala opened on Dec 24, 2019

ROM bug

Status: Open.

#7 In Logisim-Ita/Logisim;

· argjenddalti opened on Oct 18, 2018

Tick Frequency

Status: Open.

#6 In Logisim-Ita/Logisim;

· StuartP119 opened on Jun 15, 2018