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[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management #11401

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Merged
Rbb666 merged 1 commit into from
May 19, 2026
+24 −7
Merged

[libcpu][arm][cortex-m33] allows rewrite to interrupt enable/disable api to support independent interrupts management #11401

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9 changes: 8 additions & 1 deletion libcpu/arm/cortex-m33/context_gcc.S
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
* Copyright (c) 2006-2026, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
Expand All @@ -10,6 +10,7 @@
* 2013-06-18 aozima add restore MSP feature.
* 2013-06-23 aozima support lazy stack optimized.
* 2018-07-24 aozima enhancement hard fault exception handler.
* 2026-05-19 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
*/

/**
Expand All @@ -34,6 +35,7 @@
* rt_base_t rt_hw_interrupt_disable();
*/
.global rt_hw_interrupt_disable
.weak rt_hw_interrupt_disable
.type rt_hw_interrupt_disable, %function
rt_hw_interrupt_disable:
MRS r0, PRIMASK
Expand All @@ -44,6 +46,7 @@ rt_hw_interrupt_disable:
* void rt_hw_interrupt_enable(rt_base_t level);
*/
.global rt_hw_interrupt_enable
.weak rt_hw_interrupt_enable
.type rt_hw_interrupt_enable, %function
rt_hw_interrupt_enable:
MSR PRIMASK, r0
Expand Down Expand Up @@ -258,6 +261,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I

/* clear the BASEPRI register to disable masking priority */
MOV r0, #0x00
MSR BASEPRI, r0

/* ensure PendSV exception taken place before subsequent operation */
DSB
ISB
Expand Down
11 changes: 8 additions & 3 deletions libcpu/arm/cortex-m33/context_iar.S
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
;/*
; * Copyright (c) 2006-2018, RT-Thread Development Team
; * Copyright (c) 2006-2026, RT-Thread Development Team
; *
; * SPDX-License-Identifier: Apache-2.0
; *
Expand All @@ -11,6 +11,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2026-05-19 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */

;/**
Expand Down Expand Up @@ -39,7 +40,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
;/*
; * rt_base_t rt_hw_interrupt_disable();
; */
EXPORT rt_hw_interrupt_disable
PUBWEAK rt_hw_interrupt_disable
rt_hw_interrupt_disable:
MRS r0, PRIMASK
CPSID I
Expand All @@ -48,7 +49,7 @@ rt_hw_interrupt_disable:
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
EXPORT rt_hw_interrupt_enable
PUBWEAK rt_hw_interrupt_enable
rt_hw_interrupt_enable:
MSR PRIMASK, r0
BX LR
Expand Down Expand Up @@ -253,6 +254,10 @@ rt_hw_context_switch_to:
CPSIE F
CPSIE I

; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0

; ensure PendSV exception taken place before subsequent operation
DSB
ISB
Expand Down
11 changes: 8 additions & 3 deletions libcpu/arm/cortex-m33/context_rvds.S
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Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
;/*
;* Copyright (c) 2006-2018, RT-Thread Development Team
;* Copyright (c) 2006-2026, RT-Thread Development Team
;*
;* SPDX-License-Identifier: Apache-2.0
;*
Expand All @@ -10,6 +10,7 @@
; * 2013-06-18 aozima add restore MSP feature.
; * 2013-06-23 aozima support lazy stack optimized.
; * 2018-07-24 aozima enhancement hard fault exception handler.
; * 2026-05-19 Evlers allows rewrite to interrupt enable/disable api to support independent interrupts management
; */

;/**
Expand Down Expand Up @@ -39,7 +40,7 @@ NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV excep
; * rt_base_t rt_hw_interrupt_disable();
; */
rt_hw_interrupt_disable PROC
EXPORT rt_hw_interrupt_disable
EXPORT rt_hw_interrupt_disable [WEAK]
MRS r0, PRIMASK
CPSID I
BX LR
Expand All @@ -49,7 +50,7 @@ rt_hw_interrupt_disable PROC
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
rt_hw_interrupt_enable PROC
EXPORT rt_hw_interrupt_enable
EXPORT rt_hw_interrupt_enable [WEAK]
MSR PRIMASK, r0
BX LR
ENDP
Expand Down Expand Up @@ -254,6 +255,10 @@ rt_hw_context_switch_to PROC
CPSIE F
CPSIE I

; clear the BASEPRI register to disable masking priority
MOV r0, #0x00
MSR BASEPRI, r0

; ensure PendSV exception taken place before subsequent operation
DSB
ISB
Expand Down
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