TDC

Verilog implementation of a tapped delay line TDC

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
COARSECOUNTER.v		COARSECOUNTER.v
DECODESTART.v		DECODESTART.v
DECODESTOP.v		DECODESTOP.v
DNL_INL_calculation.m		DNL_INL_calculation.m
Defines.v		Defines.v
FINETDC.v		FINETDC.v
README.md		README.md
TDCMODULE.v		TDCMODULE.v
TDC_FIFO_700kHz_10000Measures.txt		TDC_FIFO_700kHz_10000Measures.txt
TDC_TOP.v		TDC_TOP.v

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