v2.3.3

• Migrated FPGA Developer AMI (Ubuntu) - 1.16.2 to Ubuntu 22.04 due to 20.04 EoL
• Added AWS Clock Gen IP toggle/deassert reset SDK API entries, Cython bindings, and updated documentation
• Updated devkit to support Vivado/Vitis tool versions back to 2024.1
• Updated AWS EC2 F2 RAB to use 32GiB of storage for the root volume to simplify building experience

v2.3.2

• Introducing a new beginner-friendly CL example called cl_axil_reg_access that demonstrates OCL AXI-Lite interface usage for CL register access
  • Interactive Jupyter Notebooks provide step-by-step instructions for the software runtime example, guiding developers through loading an AFI and performing register reads and writes on a live F2 instance
• Added IP warning suppression for Vitis builds with compatible XSAs
• General bug fixes

v2.3.1

• Released FPGA Developer AMIs - 1.19.1: Ubuntu and Rocky Linux with AMD patch AR000039913 pre-installed. This fixes the XSIM compilation bug in Vivado 2025.2, and the double compilation workaround has been removed from Makefile.common.inc
• Updated verbiage in Amazon DCV Setup Guide to improve clarity
• Updated all NPM packages in package-lock.json to address security advisories
• Added information about EC2 instance placement groups to maximize throughput and minimize latency when networking between instances in the Virtual Ethernet Application Guide
• Formatted all Python files for style, consistency, and compliance with PEP 8

v2.3.0

• Vivado/Vitis 2025.2 Support
  • Both the FPGA Developer AMI (Ubuntu) - 1.19.0 and FPGA Developer AMI (Rocky Linux) - 1.19.0 are available with 2025.2 tools installed and ready to use
  • See what's new in Vivado 2025.2 here
  • See what's new in Vitis 2025.2 here
• AWS EC2 F2 Runtime AMI Builder (RAB) Update
  • Added support for Vivado Lab Edition 2025.2
• Virtual Ethernet Driver
  • Updated to use natively-available kernel modules instead of DPDK ones
• HDK Devkit Updates
  • Cleaned up the legacy code in the power_up() simulation task to align with the correct shell clock scheme.
  • Due to a XSIM bug in Vivado 2025.2, a double compilation workaround is added in Makefile.common.inc (see ERRATA for more details)
• AFI and AMI Creation Permission Requirements
  • Added Setting Up IAM Roles for DevKit Use doc that shows how to set up an IAM role and the minimum permission configurations needed to create each of these artifacts

v2.2.2

• Introducing the AWS EC2 F2 Runtime AMI Builder (RAB)
  • The RAB is a customizable and extensible tool based on the AWS CDK that easily automates building production-ready AMIs tailored to each accelerator application's needs
  • To get started building a runtime AMI, see the README here
  • Default components are provided to modularly install specific features such as Vivado Lab Edition, the AWS CLI, the AWS FPGA SDK, and more
  • To learn how to integrate the RAB into existing AWS CDK flows, see the code example here
• Updated Rocky FPGA Developer AMI name and description to match Marketplace info
• Added F2 AFI Manifest specification for the version number, ID, and clock parameters
• Added new "--no-encrypt" build option to the HDK flow to facilitate source code debugging
• Updated fpga_clkgen_util and sde_examples with better error handling procedures, addressing stability issues found on Rocky Linux.

v2.2.1

• Release of FPGA Developer AMI 1.18.0 (Rocky Linux 8.10) with Vivado/Vitis 2025.1 tools pre-installed
• Release of Vivado HLx flow
• Fixed TCL glob expression to properly read both .sv and .v files. Credit to @pyz-creeper and @dsw for this update!
• Updated error codes in create-fpga-image for unsupported design logic
• Updated the Virtual Ethernet Application to write the DMA buffer descriptors using the byte alignment required by the CL_SDE example, preventing data alignment errors on Rocky
• Added Amazon FPGA Image (AFI) creation Python script
• Updated XRT version which includes stability fixes for Vitis

v2.2.0

• Release of Vivado/Vitis 2025.1 Tools on FPGA Developer AMI 1.18.0 (Ubuntu)
• Introduced MSI-X PCIe Interrupts Guided Example
• Added Loopback performance test for CL_SDE
• ReadTheDocs navigation improvements

v2.1.2

• Introduced Python Bindings to the SDK
• Added documentation for Python binding usage and setup
• Examples demonstrating Python-based FPGA control
• Added link to instructions for DCV licensing setup. Credit to @morgnza for this update!
• Added verbiage to DCV setup guide to show where to set virtual display resolution
• Fix to Bandwidth Calculation

v2.1.1

• Added global register offset for the SDE IP.
• Added CL_SDE software exmaple for a user allocated DMA buffer.
• Documentation to assist F2 customers with releasing AFIs and AMIs on the AWS Marketplace.
• Documentation to assist in creating a virtual desktop based on the FPGA Developer AMI running graphics-intensive applications remotely on Amazon EC2 instances.
• Fixed the BW calculation and tolerance calculation in the test_hbm_perf_random in the cl_mem_perf.

v2.1.0

Support for Vivado and Vitis 2024.2 tools.
Releasing New Developer AMI for 2024.2 tools.
Updating the asynchronous fpga_mgmt_examples to poll each FPGA once before moving to the next.