Dynamic Instruction Scheduler

A cycle-accurate simulator of a superscalar out-of-order processor pipeline written in C++. Models the full 9-stage dynamic scheduling pipeline — from fetch through retire — with a configurable pipeline width, Reorder Buffer (ROB), and Issue Queue (IQ). Produces per-instruction timing traces and an overall IPC measurement.

Pipeline Stages

Fetch → Decode → Rename → Register Read → Dispatch → Issue → Execute → Writeback → Retire

Stage	Description
Fetch	Reads up to WIDTH instructions per cycle from the trace file
Decode	1-cycle decode; instructions stall until the bundle drains
Rename	Allocates ROB entries; renames source registers via the Register Map Table (RMT); stalls if ROB is full
Register Read	Checks for forwarded ready values from the ROB; 1-cycle stage
Dispatch	Writes instructions into the Issue Queue; stalls if IQ is full
Issue	Selects up to WIDTH oldest ready instructions (both source tags resolved) and fires them to Execute
Execute	Runs instructions for their full execution latency (type 0: 1 cycle, type 1: 2 cycles, type 2: 5 cycles); broadcasts wakeup to dependent IQ/pipeline entries on completion
Writeback	Marks the ROB entry as ready (1 cycle)
Retire	Commits up to WIDTH instructions in order from the ROB head; frees RMT entries

Key Structures

• ROB (Reorder Buffer) — circular buffer indexed by a head/tail pointer; holds in-flight instructions for in-order retirement
• RMT (Register Map Table) — 67-entry table mapping architectural registers to ROB tags; valid bit cleared on retire
• Issue Queue — vector of in-flight instructions waiting for operand readiness; wakeup logic clears source tags on execute completion

Build

Requires g++ and make.

make

Produces the sim binary.

Usage

./sim <ROB_SIZE> <IQ_SIZE> <WIDTH> <trace_file>

Parameter	Description
ROB_SIZE	Number of ROB entries (e.g. 256)
IQ_SIZE	Number of Issue Queue entries (e.g. 64)
WIDTH	Fetch/decode/issue/retire width per cycle (e.g. 4)
trace_file	Path to instruction trace file

Example

./sim 256 64 4 gcc_trace.txt

Trace File Format

Each line represents one instruction:

<hex_pc> <op_type> <dest_reg> <src1_reg> <src2_reg>

• op_type: 0 = 1-cycle ALU, 1 = 2-cycle multiply/load, 2 = 5-cycle FP/divide
• Register index: -1 means no register (unused operand/destination)

Example:

00a08400 0  1  2  3
00a08404 1  5 -1  6
00a08408 2 -1  1  5

Output Format

For each retired instruction, one line is printed:

<seq#> fu{<type>} src{<s1>,<s2>} dst{<d>} FE{<start>,<dur>} DE{...} RN{...} RR{...} DI{...} IS{...} EX{...} WB{...} RT{...}

Followed by a summary:

# === Processor Configuration ===
# ROB_SIZE = 256
# IQ_SIZE  = 64
# WIDTH    = 4
# === Simulation Results ========
# Dynamic Instruction Count    = 1000000
# Cycles                       = 412573
# Instructions Per Cycle (IPC) = 2.42

Implementation Notes

• Wakeup propagation: when an instruction completes Execute, its ROB tag is broadcast to clear matching source tags in the IQ, dispatch bundle, and register-read bundle — enabling pipelined wakeup without stalling
• In-order retirement: the ROB head is only advanced when the head entry's ready bit is set, enforcing precise exception semantics
• Width-limited stages: Fetch, Issue, and Retire are all bounded by WIDTH per cycle; Rename and Dispatch stall the entire bundle if structural hazards exist

Technologies

• Language: C++ (C++11)
• Build: GNU Make + g++
• Standard libraries: <iostream>, <vector>, <algorithm>, <cinttypes>