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Update to latest Spike version#87

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jmgorius wants to merge 2 commits intochipsalliance:mainfrom
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Update to latest Spike version#87
jmgorius wants to merge 2 commits intochipsalliance:mainfrom
jmgorius:main

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@jmgorius
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@jmgorius jmgorius commented Mar 2, 2026

Disable DTB discovery, which was introduced in riscv-software-src/riscv-isa-sim@2c94ea4

Disable DTB discovery, which was introduced in riscv-software-src/riscv-isa-sim@2c94ea4
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I verified this fix locally. Adding the false argument to the sim_t constructor is required for compatibility with the latest Spike. My riscv-vector-tests build is now passing Stage 1 and Stage 2 with this change.

@nadime15
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Could you update the hash and pull the latest? Since then, two new vector extensions, Zvabd and Zvzip, have been added (not yet ratified) to Spike, along with a fix to the RVV Crypto group.

@jmgorius
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Sure! I checked locally, and no other API changes seem to have occured.

@ksco
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ksco commented Apr 1, 2026

There are failures in the RV64_Zvl64 combo.

@jmgorius
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jmgorius commented Apr 1, 2026

There are, but I have no clue why this particular check would fail when the others all succeed. Maybe someone with more experience with the project may have some insights?

@nadime15
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nadime15 commented Apr 1, 2026

@jmgorius Unfortunately, I don’t have a straightforward fix to propose. However, if you have the time, I would suggest gradually replacing the current spike hash with older ones and checking which version still passes. This should help narrow down where things start to break.

In the Makefile, you can provide a PATTERN. For now, generating cases only for vmulh_vv should significantly speed up testing and make it easier to isolate the issue.

@jmgorius
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After some bisecting, it turns out that this Spike commit is the culprit: riscv-software-src/riscv-isa-sim@d1e34d0

I am trying to figure out how to fix the issue.

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4 participants