Support for verilator 5 (require v5.026 or later)

[reo-pon]

This pull request adds the following features:

• The Verilog testbench (TestMain.sv) is simulated directly using the timing support feature introduced in Verilator v5. However, this requires Verilator version v5.026 or later.
• The old testbench files for Verilator have been removed from this repository.
• To improve simulation performance in Verilator, the method for filling memory as dummy data has been modified.
• Additionally, an issue that prevented simulation in Vivado has been fixed.