linalg: reusable CPU cache-size detection module - #2349
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The single-thread MMM block-budget probed L2 with detection logic inlined in frame/mmm/mod.rs, reusable nowhere and limited to macOS/Linux L2. Move it into a cache module that exposes L1d/L2/L3 through one memoised probe (macOS/iOS via sysctlbyname, Linux/Android via /sys, Windows via wmic) and have the block budget read it. The existing L2 budget is unchanged. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This was referenced Jun 7, 2026
kali
approved these changes
Jun 19, 2026
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doing some cleanup: @kali : keep or close? |
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I'm interested. It's an enabler for matmul sizing optims. So I say keep. Don't read too much into my limited pace at looking and integrating. It's not lack of interest, it's limited bandwidth. |
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Factors the L2 cache-size probe that drives the single-thread MMM block budget out of
frame/mmm/mod.rsinto a small, reusablecachemodule, so other heuristics (im2col lowering thresholds, kernel dispatch, future K-blocking) can read the same memoised numbers instead of re-implementing a platform probe.cache::cache_info()returns L1d / L2 / L3 (bytes;0= undetected) from one lazily-detected, process-cached probe: macOS/iOS viasysctlbyname(FFI, replacing the previoussysctlsubprocess;hw.perflevel0.*preferred on hybrid Apple Silicon), Linux and Android via the/syscache walk keyed off each entry's reported level+type, and Windows viawmic.block_budget_bytesnow readscache_info().l2; the existing L2 budget formula and the 256 KiB unknown-cache fallback are unchanged, so single-thread blocking behaviour is preserved. Honest0-on-unknown semantics with*_or_defaulthelpers for callers that want an arch-based guess.Verified on Apple M-series (L1d 128 KiB, L2 12 MiB, L3 not exposed → reported 0): full
tract-linalgsuite green,cargo fmt --allclean, no new clippy findings.Citations for the runtime cache-size detection driving blocking:
Eigen queryCacheSizes() (Eigen/src/Core/util/Memory.h) — runtime L1/L2/L3 via CPUID (x86) / sysctl-sysconf, ~0.5 ms once per process. Direct analog of this module. (ref)
glibc sysconf(_SC_LEVELx_CACHE_SIZE); x86 CPUID leaf 0x04/0x18; Linux sysfs cacheinfo (drivers/base/cacheinfo.c); ACPI PPTT (ARM cache topology).
hwloc (Portable Hardware Locality) — cross-platform topology incl. shared/last-level caches.
Note this PR does not make hwloc a dependency, but borrows the idea from it