This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

A VHDL code base that contains Utility Packages for both HDL and Testbenches

4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

Implementation of 4-bit Arithmetic Logic Unit using structural modeling in Verilog. Features 8 operations controlled by 3-bit select line. Simulated on EDA Playground with waveform analysis.

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

5-stage MIPS pipeline CPU in Verilog with data forwarding, hazard detection and full instruction set. Simulated on EDA Playground.

UART communication system in Verilog featuring transmitter, receiver, baud rate generator, self-checking testbench, and comprehensive verification using EDA Playground.

Synchronous FIFO implementation in Verilog with testbench and simulation waveforms

Advanced VLSI Digital Clock in Verilog (RTL) featuring hardware debouncing, alarm FSM, and a real-time Python/Tkinter GUI dashboard via UART.

UART Transmitter/Receiver in Verilog - 9600 baud, 8-bit, full loopback tested. Simulated on EDA Playground with Icarus Verilog.

SystemVerilog verification of an 8-bit × 16 synchronous FIFO using a class-based testbench, scoreboard, and 10+ SVA assertions.

Verilog HDL implementation of a 5-stage pipelined RISC-V processor with Hazard Detection and Forwarding Unit verified using EDA playground and EPWave.

A parameterized (8/16/32-bit) Low-Power ALU in Verilog featuring structural Operand Isolation and register-level Clock Gating to minimize dynamic power dissipation ($P_{dynamic}$). Simulation-ready for EDA Playground and Icarus Verilog.

8-bit CPU in Verilog - implements fetch-decode-execute cycle with custom ISA, simulated using Icarus Verilog

A 4-bit Arithmetic Logic Unit (ALU) implemented in Verilog HDL with Carry, Zero, Overflow, and Negative status flags. Verified using EDA Playground and EPWave.

30-day VLSI & Digital Design learning journey — Verilog, FSM, FPGA, UART

UVM extension for JSON transaction recording and waveform visualization — runs on EDA Playground or locally