Add wolfBoot FIT support for loading bitstream#786
Open
dgarske wants to merge 1 commit into
Open
Conversation
dgarske
force-pushed
the
fit_fpga_bitstream
branch
from
134b701 to
a5d0255
Compare
dgarske
force-pushed
the
fit_fpga_bitstream
branch
from
a5d0255 to
ab6b3b4
Compare
Comment on lines
+1240
to
+1245
| /* Select full vs partial reconfiguration from the U-Boot-style | ||
| * "compatible" string (e.g. "...fpga-partial"). Default is full. */ | ||
| comp = fit_get_compatible(fdt, fpga_node); | ||
| if (fit_str_contains(comp, "partial")) { | ||
| flags = HAL_FPGA_PARTIAL; | ||
| } |
Comment on lines
+972
to
+979
| /* 8. Wait for the PL to report configuration complete. */ | ||
| t0 = hal_get_timer_us(); | ||
| while (!(Z7_DEVC_INT_STS & Z7_DEVC_INT_PCFG_DONE)) { | ||
| if (hal_get_timer_us() - t0 > Z7_FPGA_TIMEOUT_US) { | ||
| wolfBoot_printf("Z7 FPGA: timeout waiting PCFG_DONE\n"); | ||
| return -1; | ||
| } | ||
| } |
Comment on lines
+1753
to
+1757
| /* Confirm the PL reports configured (PCAP status). */ | ||
| memset(ret_payload, 0, sizeof(ret_payload)); | ||
| pmu_request(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload); | ||
| wolfBoot_printf("FPGA status: 0x%x\n", ret_payload[1]); | ||
|
|
Comment on lines
+342
to
+345
| # FIT fpga-subimage discovery (fit_find_images / fit_get_compatible). | ||
| unit-fit-fpga: ../../include/target.h unit-fit-fpga.c | ||
| gcc -o $@ unit-fit-fpga.c $(CFLAGS) -DWOLFBOOT_FDT \ | ||
| -ffunction-sections -fdata-sections $(LDFLAGS) -Wl,--gc-sections |
dgarske
force-pushed
the
fit_fpga_bitstream
branch
from
ab6b3b4 to
fcc8bc3
Compare
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Features
fpgasub-image in a signed FIT, using the standard U-Boot convention: sub-imagetype = "fpga", configurationfpga = "<node>"reference, and acompatiblestring selecting the load method (partialin the string selects partial reconfiguration, otherwise full). Programmed before the kernel/DTB load so PL-dependent clocks/peripherals come up first.hal_fpga_load()HAL abstraction with a weak default (returns not-implemented) and per-target implementations.TARGET=zynq): full bitstream via the PMU firmwarePM_FPGA_LOADEEMI call (xilfpga / CSU DMA / PCAP).TARGET=zynq7000): full bitstream via a new DevC/PCAP DMA driver (UG585 ch.6) with bounded poll-loop timeouts.TARGET=versal): documented not-implemented stub (PL config is a PLM Load-PDI IPI).fit_load_fpga()stages the bitstream to a configurable DDR address (WOLFBOOT_LOAD_FPGA_ADDRESS), decompressing gzip bitstreams (the typicalmkimageoutput, which has noloadproperty) bounded byWOLFBOOT_FIT_MAX_FPGAand validated by the gzip CRC32 + ISIZE.FIT_CONFIG_SELECT=1plus a weakhal_fit_config_name()hook lets an integrator boot a non-defaultconfiguration (e.g.conf-<board>); the default returns NULL (use the FITdefault). No board-detection (GPIO/CHIPID) logic is shipped upstream.FPGA_BITSTREAM,FPGA_NONFATAL(failed PL load warns and continues instead of panicking),WOLFBOOT_LOAD_FPGA_ADDRESS,FIT_CONFIG_SELECT. All opt-in; default builds are unchanged.fit_find_images()extended to discover the fpga node (configfpgaproperty andtype == "fpga"fallback); newfit_get_compatible()helper.unit-fit-fpgaunit test covering fpga discovery and compatible parsing; docs and.itstemplate updated.Fixes
PM_FPGA_LOADsize is passed in bytes (not 32-bit words), matching stock Xilinx U-Boot and the PMU firmware xilfpga, which divides by the word length internally.loadproperty to the staging address, instead of failing closed.hal_fpga_load()/hal_fit_config_name()defaults inhal/hal.c(linked into every target) rather than a region oflibwolfboot.cthat is compiled out for the Xilinx targets, fixing an undefined-reference link error.